搜索资源列表
CRC
- 这个是我花了一个星期的CRC算法，有并行与串行的区别与时序的分析。。。。希望站长能够同意-This is a week I spent the CRC algorithm, there is the difference between parallel and serial and timing analysis. . . . Hope that regulators can not agree
TimingAnalysis
- 这是有关FPGA时序分析的一个实验步骤，欢迎大家下载啊-This is the FPGA timing analysis of an experimental procedure
TimeQuestxuexi
- TIMEQUEST学习的好资料，可以教会大家如何使用ALTERA的时序分析工具-TIMEQUEST learning good information, can teach you how to use timing analysis tool ALTERA
123
- 华为_静态时序分析与逻辑设计，FPGA时序分析友-Huawei _ static timing analysis and logic design, FPGA timing analysis of Friends
PerfectTiming
- 完美时序，含中英文两个版本！这应该是FPGA时序分析方面最经典最权威的书了，相信会对FPGA爱好者有很大用处！-Perfect timing, with two versions in English! This should be the most classic FPGA timing analysis the most authoritative book, that would be very useful FPGA lovers!
modelsim-timing-analysis
- 自己整理的一个关于如何使用modelsim进行功能仿真，时序仿真和布局布线的后仿真的文档，例子是抄的，针对的版本是modelsim se6.2b-Their finishing a feature on how to use modelsim for simulation, timing simulation and post-layout simulation of the document, copy the example is for the version of modelsim se
analysis
- 很经典的华为时序分析资料，用于电路的时序分析-Huawei is the classic time series analysis data for circuit timing analysis
Lattice_FPGA
- 该使用指南适用于初次使用ispLEVER 软件或者不常使用该软件的工程设计人员，它可以帮助你去了解 不同的处理过程，使用各种工具，以及熟悉ispLEVER 产生的各种报告。在进行下一步时，可以准备一 个设计，以此去了解设计的仿真，功耗的计算，静态时序分析，以及以时序驱动的布局和布线，检查由 软件输出的报告等。以此设计为例，你可以练习约束设计的输入，输出信号以及这些信号管脚的分配去 满足系统要求。也可以修改约束条件，达到最佳地利用LatticeEC 的结构和资源，同时实现高性能。该
13.SeqCktTiming
- Sequential timing of digital circuits, timing analysis basics.
Verilog_HDLtiming-.
- Verilog_HDL_那些事儿_时序篇 。详细介绍了Verilog HDL的时序分析和设计-Verilog_HDL_ thing _ that the timing articles. Details of the Verilog HDL timing analysis and design
FPGA
- FPGA设计中的时序分析及异步设计注意事项 -FPGA design timing analysis and design considerations for asynchronous
D1
- ALTERA 时序分析资料 Timequest 基础知识-ALTERA the basics of timing analysis data Timequest
huawei
- 华为内部资料，内容为静态时序与逻辑分析，对IC前端设计有用-Huawei internal information content of static timing analysis and logic, the IC front-end design useful for
sram1
- 这个是FPGA最简单控制SRAM的方法之一，可以直接嵌套到你们的代码中，建议先看时序分析-This is the simplest control SRAM FPGA one of the methods can be nested directly to your code, look at the timing analysis proposed
6c8ec37a-3fd5-41e1-b3cf-a88af5f7c888
- 《华为静态时序分析与逻辑设计》《华为静态时序分析与逻辑设计》-Huawei static timing analysis and logic designHuawei static timing analysis and logic design
Timing-analysis
- FPGA玩转Altera之时序篇，包括时序分析注意事项-Altera play the FPGA XuPian, including timing analysis the matters needing attention
Hua-Wei-ASICaVerilogaHardware
- 华为内部资料，整理分享给大家，内容如下： 1.Proverilog编码规范(草案) 2.华为_Verilog HDL电路设计指导书 3.华为内部培训资料linux 基础 4.华为同步电路设计规范 5.华为-硬件工程师 6.静态时序分析与逻辑设计- Huawei internal books, organize to share to you, reads as follows: 1.Proverilog coding standard (draft) 2.th
Timing-Analysis
- 关于VHDL/VERILOG进行EDA设计时序分析时需要注意的一些需要注意的问题及处理策略，保证相当实用，请需要的人参考-VHDL/VERILOG the EDA design timing analysis need to pay attention to some issues that need attention and treatment strategies, guaranteed to be quite practical, please need Reference
Timing
- 国外关于时序设计的一本非常好的书，写得非常详细，包括时序的分析的原理-Abroad on timing design of a very good book, written in great detail, including the principle of timing analysis, etc.
IO-timing-constrain-in-fpga
- 对FPGA的IO口的时序分析小结，能够详细理解其约束时序规则-FPGA timing analysis summary of IO port, capable of a detailed understanding of its timing constraint rules