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allot1_4
- 设计一个双1路到4路的数据分配器电路 设计要求: (1)1路到4路数据分配器其逻辑功能表如表3.2.2所示,试用行为描述方式写出设计块对其逻辑功能进行描述。 表3.2.2 数据分配器功能表 S1 S0 Out0 Out1 Out2 Out3 0 0 in z z z 0 1 z In Z Z 1 0 Z Z In z 1 1 Z Z Z in-1 way to design a dual 4-way data distributor circuit design
shizizhong
- 利用QuartusII7.0、MATLAB以及SmartSOPC实验系统进行多功能数字钟的设计是本次试验的主要内容。该数字中需包含的功能主要有:分频、校时校分、清零、动态显示、整点报时、闹钟闹铃、秒表以及24小时制和12小时制的转换等。-QuartusII7.0, MATLAB, and SmartSOPC experimental system for the design of multi-function digital clock is the main content of the t
stack
- 设计了一个深度为64,字长为16_bit堆栈,要求有栈空、栈满和栈溢出信号。试以双向移位寄存器结构或存储器结构的电路结构方式设计完成电路,并说明它的特点。-Designed with a depth of 64, the word length is 16_bit stack, stack empty, stack full and stack overflow signal. Trial to the way of bi-directional shift register or memory
Digital-stopwatch
- 数字秒表,用VHDL语言描述,用层次设计概念,将设计任务分成七个子模块,规定每一模块的功能和各模块之间的接口,然后再将各模块合起来形成顶层文件联试。-Digital stopwatch, using VHDL descr iption, level design concept, the design task is divided into seven sub-module to provide the interface between each module functions and m
key_scan_design
- 按键控制试验 verilog编写,详细描述了怎么来控制开发板上的按键-Key controlled trial verilog written, detailed descr iption of how to control the development board buttons
DA_TLC5620
- 这是用verilog写的基于FPGA的TLC5620串行DA的驱动代码,稍加修改后试用于通常的串行DA的驱动-This is a FPGA-based verilog write driver code TLC5620 serial DA, the latter slightly modified the trial in an ordinary serial DA driver