搜索资源列表
V3(2)
- 设计一个7段数码管译码器，带数码管的4位可逆计数器 [具体要求] 1. 7段数码管译码器 使用拨码开关SW3, SW2, SW1, SW0作为输入，SW3为高位，SW0为低位。 将输出的结果在HEX1，HEX0显示。当输入为‘0000’~‘1111’显示为00~15， 2. 带数码管的4位可逆计数器 将实验三的结果在数码管上显示。结合上次实验，将4位可逆计数器，数码管显示，分别作为两个子模块，实现在数码管上显示的4位可逆计数器。-Design of a 7-s
KB-1B-Programs-V3.0
- kb1b开发板配套程序，ASCII码表和液晶图片，程序目录，有Cry1602，蜂鸣器，模数转换，TFT等等。-kb1b development board supporting the program, ASCII code table and the LCD image, the program directory, there Cry1602, buzzer, analog-digital conversion, TFT, and so on.
8051_ADC
- AT89C51 Based ADC Program using keil v3. Very useful.-AT89C51 Based ADC Program using keil v3. Very useful.
auk_rtprx-v3.1.0.tar
- The Altera(R) RTP Receiver function implements a buffer for received RTP packets. Duplicated and re-ordered packets are corrected. Missing packets can be fixed using Pro-MPEG Code of Practice #3 Forward Error Correction
auk_udpipmac-v3.3.0.tar
- The Altera(R) UDP/IP function implements a hardware solution for the transmission and reception of UDP/IP encapsulated network traffic.
I2C_control
- Xilinx提供的I2C控制器代码,Master/Slave全功能- Readme File for I2C Customer Pack Created: 7/8/99 ALS Revised: 11/4/99 ALS ******************************************************************************************************************************
TFTtest-Li
- verilog ils9325 v3.08 controller, driver
V3.0-VerilogHDL
- VerilogHDL那些事儿V3.0 详细生动的介绍了Verilog HDL。-V3.0 VerilogHDL those things more lively introduction to the Verilog HDL.
VerilogHDL-V3.0
- 这是一本讲述verilogHDL的书籍，通俗易学，名字是《VerilogHDL那些事儿》-This is a book about verilogHDL, popular easy to learn, the name is " VerilogHDL that thing"
mhd-v3.388
- 霓虹灯设置小程序，通过本软件可以设置霓虹灯显示。-Settings applet neon, neon lights can be set through the software display.
v3-1-4-12
- A Novel VLSI Architecture of Hybrid Image Compression Model based on Reversible Blockade Transform
Enc_With_Punc---2011-11-28-v3.0
- Viterbi 译码打孔和去打孔代码, ,VERILOG 代码，自己写的，包含时钟打孔，-Viterbi Decoder With Puncture and Depuncture， Verilog Code，clock puncture ,
Mojo-Hexapod-Blob
- Verilog library for Mojo V3 FPGA development board
v3
- mojo v3 complete eagle schematic
can_v3_2
- XILINX 的IP核CAN V3.2的VHDL程序(XILINX's IP core: CAN_V3.2-VHDL)