搜索资源列表
ALU
- vhdl代码 使用quartus编译 cpu中 alu的设计 可作为课程设计的参考 此为16的运算器-VHDL code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
CPU
- 一个多周期CPU的完整设计，quartus平台，Verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
duozhouqiCPU
- VHDL 多周期CPU设计。基于Quartus II平台-VHDL design of multi-cycle CPU. Quartus II-based platforms
Microprogramcontroller
- 微程序控制器部件实验，使用VHDL语言使用Quartus测试通过，模拟CPU-Micro-program controller component experiments, the use of VHDL language use Quartus test, simulation CPU
mips
- MIPs CPU，VERILOG代码，经过QUARTUS综合，时序分析，验证无误。-MIPS CPU
danzhouqiCPU
- VHDL单周期CPU设计,基于Quartus II 开发平台-VHDL single-cycle CPU design, Quartus II development platform based on
parallel-output-controller-(POC)
- 并行输出控制器，实现CPU与打印机之间的通信，程序基于VHDL语言，内附完整实验报告与仿真图像-The purpose of this project is to design and simulate a parallel output controller (POC)which acts an interface between system bus and printer. The Altera’s Quartus II EDA tool is recommended and provid
cpu
- 一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
altera_inspector.log
- vhdl代码 使用quartus编译 cpu中 alu的设计 可作为课程设计的参考 此为16的运算器-VHDL -code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
CPU-with-VHDL-16-32
- 在quartus中运行的32位指令集的16位CPU程序，模块化设计，包括MBR, BR, MR, ACC, MAR, PC, IR, CU, ROM, RAM, ALU等模块-In the the quartus run 32 16-bit CPU instruction set procedures, modular design, including the MBR, BR, MR, the ACC, the MAR, the PC, the IR CU, the ROM, RAM, ALU
liushuixianCPU
- VHDL 流水线CPU的设计，基于Quartus II平台-VHDL design of pipelined CPU based on Quartus II platform
CPU
- 运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。-Using vhdl hardware descr iption language developm