搜索资源列表
Convolutional encoding and Viterbi decoding with k
- 卷积码编码和维特比解码 当K为7 时 供大家参考Convolutional encoding and Viterbi decoding with k 7 rate 1 2 -convolutional coding and Viterbi decoding when K 7:00 for reference convolutional encoding and Viterbi decoding with k 1 2 7 rate
viterbi.rar
- 这是一个用VERILOG HDL语言编写的viterbi译码程序,This is a language VERILOG HDL by the viterbi decoding process
Viterbi
- 实现VHDL的维特比译码 -VHDL Viterbi decoding to achieveVHDL Viterbi decoding to achieve
ViterbiDecodeK9R12HardDecision
- viterbi 硬判决译码，基本实现了（2，1，9）卷积码的硬判决译码，用modelsim RTL仿真通过-hard-decision viterbi decoding, the basic realization of the (2,1,9) convolutional codes hard decision decoding, using modelsim RTL simulation through
husw
- 用VHDL语言设计维特比 解码器 是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation
VB_decode
- Viterbi译码的VHDL代码，并且附有详细说明-Viterbi decoding of the VHDL code, and accompanied by a detailed descr iption
viterbi
- 硬判决viterbi译码的硬件实现，通过verilog语言。采用回溯的方法。回溯深度为16.-Hard decision viterbi decoding in hardware, through the verilog language. A retrospective approach. Back depth is 16.
Viterbi_check
- It is a verilog code for viterbi decoding with trellis diagram
Viterbi_verilog
- 在ISE环境下用Verilog语言编写的卷积码程序及Viterbi译码程序-Under the ISE Verilog language with procedures and Viterbi convolutional code decoding program
viterbi
- 高效率的viterbi译码，对通信中的卷积码进行译码-Efficient viterbi decoding of communications for decoding convolutional codes
finial_test
- 卷积码和Viterbi译码的源程序，在Xilinx ISE环境下使用Verilog编写，有助于卷积码和Viterbi译码的学习-Convolutional codes and Viterbi decoding of the source, in the Xilinx ISE environment, use of Verilog prepared to help convolutional codes and Viterbi decoding of the study
encoder
- 802.11a卷积码的实现，使用公式133和177，可以用标准viterbi解码-802.11a convolutional code to achieve, using the formula 133 and 177, you can use standard viterbi decoding
Design-Space-Exploration-of-Hard-Decision-Viterbi
- Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation
viterbi
- 维特比译码，卷积编码，verilog编写，2,1,2编码-Victor than decoding, convolution code, verilog write, 2,1,2 coding
cConnvolutiono
- 卷积码编码与维特比解码 当K为7 时 供大家参考-convolutional encoding and Viterbi decoding with k 1 2 7 rate
convotion_decode
- 用verilog写的卷积码的编码程序以及viterbi译码程序-Use verilog write convolution code coding procedures and viterbi decoding program
viterbi-ip-core-using-mothed
- FPGA的Viterbi译码器IP 核的使用说明，简单方便，一目了然。还能进行tcm译码，功能强大呀-Instructions for use of the FPGA Viterbi decoder IP core, easy glance. Can tcm decoding powerful!
conv_dencode
- 基于quartus软件的卷积译码算法，应用维特比译码算法完成-Convolutional decoding algorithm based on the quartus software.complete the application of viterbi decoding algorithm
weitebi_notes
- 维特比译码 ，说明比较详细， 用于卷积的译码，很不错-Viterbi decoding, a more detailed descr iption
viterbia
- 实现viterbi译码，通过比较最小汉明距来判别最佳路径，删除不必要的路径，最终找到最佳路径。-Implement viterbi decoding, by comparing the minimum hamming distance to distinguish the best path, delete unnecessary path, finally find the best path.