搜索资源列表
test2_fpga_led
- 基于FPGA_cycloneIV代FPGA的简单程序,含管脚配置文件。实现了IO的控制。可以点亮一个LED灯。-Based on a simple program FPGA_cycloneIV behalf of the FPGA, including pin configuration files. Realized IO control. You can light up a LED lamp.
Quartus_II
- verilog学习FPGA的基础教程,希望能够帮助您,-FPGA-based tutorial learning, we hope to help you
des3
- 基于FPGA的des3加密算法,在QuartusII环境下编译-Encryption algorithm of des3, built under QuartusII
Actel_Smartfusion_MSS_APB3_Master
- Actel Smartfusion FPGA芯片APB3总线示例程序-Actel Smartfusion FPGA chip AHB3 bus sample program
A5
- A5算法仿真,毕设用的,FPGA平台,digilent的,用的是vhdl语言-The A5 algorithm simulation, never put off till tomorrow what you can put to use, the FPGA platform, digilent, using VHDL language
lcd1602
- FPGA控制lcd1602液晶显示,使用Verilog语言在quartus II环境下开发-FPGA lcd1602 verilog
source_tx
- FPGA控制uart 串口发送,使用Verilog语言在quartus II环境下开发-uart tx FPGA verilog
source_ps2
- FPGA控制PS2协议,使用Verilog语言在quartus II环境下开发-FPGA PS2 Verilog
source_ds1302
- FPGA控制ds1302,使用Verilog语言在quartus II环境下开发-FPGA verilog ds1302
ram
- 此代码可以是FPGA内部ram存储器在读取一系列数据后,然后每间隔1秒钟读出来。-This code can be read in the FPGA internal ram memory after a series of data, and then read out at intervals of 1 second.
LogicAnalyzers
- 全套逻辑分析仪资料,包括:PCB、FPGA源码、MCU源码,说明书。可以直接生产使用-A full set of logic analyzer data, including: PCB, FPGA source code, MCU source, instruction manual. You can use the direct production
9_eeprom_test
- 基于Cyclone IV系列FPGA的eeprom驱动程序,Verilog语言编写。-eeprom driver based Cyclone IVhardware,use VerilogHDL.
buzzer
- 采用FPGA编写程序控制蜂鸣器,实现音乐播放-Using FPGA program to control the buzzer to achieve music playback
SAKURA_Checker_release_20130902
- SAKURA-G FPGA开发板上位机源代码-SAKURA-G FPGA development board host computer source code
piso8_ok_bingchuanzhuanhuan
- 本程序是用vhdl开发的实现并串转换功能的程序。(This procedure is developed using VHDL implementation and string conversion function of the program.)
FPGA_SOURCE_CODE
- ad9910 FPGA VERILOG 初始化代码,(Ad9910 FPGA VERILOG initialization code)
四分频器
- 使用FPGA实现单一频率信号分频为原来的1/4
bcd
- FPGA实现3-8译码器用于实验测试,非常适合于初学者(FPGA implementation decoder)
AESj 加密解密Verilog
- 128位AES加密解密,可以在FPGA上实现
dynamic control xilinx fpga
- 文件中,有赛灵思动态配置PLL的相关代码,用户可以通过DCP 接口对pll的输出频率 动态设置