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seven_seg
- 一个verilog代码，该代码很适合初学者熟悉FPGA的开发流程，主要功能为实现七段代码管的显示，主要针对xilinx公司spartan3系列的FPGA-a verilog code that are very suitable for beginners FPGA familiar with the development process, main function of the realization of the code in paragraph 107, xilinx against
xilinx Virtex-4 fpga开发板
- xilinx Virtex-4 fpga开发板（ML402,ML403等）的使用入门手册,xilinx Virtex-4 fpga development board [ML402, ML403, etc.] Getting Started Manual
NEXYS2_Tutorial
- A tutor for beginner to start on a DIGLINE NEXY2 broad with Xilinx spartan3E, shows how to implement a code in to the FPGA broad.
61IC_S4182
- 基于FPGA设计工具Xilinx ISE 编写的程序代码-Xilinx ISE FPGA-based design tools to write program code
Taximeter
- 出租车计价器（其中包括分频模块，计程模块，计时模块，计费模块，显示模块以及顶层模块），基于Verilog HDL语言，开发板是FPGA(Sparten 6 LXS45),开发环境是Xilinx。-Taxi meter (including frequency module, the meter module, timing module, billing module, display module and top-level module), based on Verilog HDL lang
ConvCodeXilinx
- This a convolutional encoder in xilinx virtex-5 ML506 board FPGA. This program use matlab for comunicating with FPGA. The convolutional encoder using rate 1/2, and 1/3.The register are 3,4,5,6 and 7.-This is a convolutional encoder in xilinx virtex-5
Xilinx_DDR2_IP_TEST
- 本文档对Xilinx 公司FPGA开发环境中ISE中如何调用DDR2 IP进行了详细的说明。直接例化IPCORE,采用无TESTBENCH，无PLL的方式.-This document FPGA from Xilinx ISE development environment how to call DDR2 IP for a detailed descr iption. Direct instantiation IPCORE, no-TESTBENCH, no PLL ways.
xapp1205-high-performance-video-zynq
- Xilinx FPGA平台Zynq ZC702下AXI vdma IP核应用工程。-An Axi vdma ip application project based on Xilinx Zynq ZC702 platform.
dynamic control xilinx fpga
- 文件中，有赛灵思动态配置PLL的相关代码，用户可以通过DCP 接口对pll的输出频率 动态设置