搜索资源列表
countqi
- 计数器 同步异步预置数清零 verilog hdl 编写-Asynchrony preset counter reset the Verilog HDL few prepared
yunsuan-verilog
- 运算器的实现，即实验指导书中的实验一，文件中包含有原代码及端口设置（可变），用vrilog HDL编程，Xilinx ISE 6仿真，并在实际电路中得到实现．-operations for the realization of the experimental guidance of a book. document contains the original code and port settings (variable), with vrilog HDL programming, Xili
trafficLight-verilog
- 交通灯状态机的实现，用verilog HDL编程，Xilinx ISE 6仿真，在实际电路中得到验证．-traffic lights to achieve the state machine, with verilog HDL programming, Xilinx ISE 6 simulation, the actual circuit have been tested.
FPGA_test_frequency
- 本原码是基于Verilog HDL语言的FPGA原程序，主要用于测频率，特点主要是可以更快地测频。实时性更高。-primitive code is based on Verilog HDL FPGA original program, mainly for the measurement frequency, the main features can be faster frequency measurement. Real-time higher.
verilogsourcefiles
- 该代码中有不少关于学习verilog HDL的例子,对初学者有帮助
Freq
- 简易数字频率计，用Verilog HDL编写的，基于Quartus II实现，结构清晰，功能较为全面，能满足简单的频率测量要求
uart
- 实现简单的UART功能,在QUARTUS4.0下编译通过,采用VERILOG HDL编写.
AD7865test1
- verilog hdl写的利用fpga控制ad7865进行多路ad数据采集的程序源代码。
uart_rx
- actel A3P250 fpga用VERILOG HDL语言实现串口功能的源代码
秒表设计
- 用verilog hdl实现的秒表程序。可以精确计时到1分，可简单修改程序后实现更长时间的计时。
fp_2
- 通过Verilog HDL编程，在CPLD上实现任意小数（分数）分频，分频系数为N+A/B.-By Verilog HDL programming, to achieve any decimal in the CPLD (score) frequency, frequency coefficient N+ A/B.
Serial
- FPGA与PC串口通信的Verilog HDL 程序-FPGA and the PC serial communication procedures Verilog HDL
1-in_clk
- Verilog HDL编写的4条指令CPU-Verilog HDL prepared four instructions CPU
veriloghdl-135
- verilog hdl教程135例-verilog源码-verilog hdl Tutorial-verilog source 135 cases
Music_LiangZhu
- FPGA音乐试验，语言：verilog HDL-A FPGA expperientation which can play music Liangzhu，language：verilog HDL
I2C19861208888
- i2c总线模拟，verilog hdl编写的总线模拟控制程序-i2c bus simulation, verilog hdl prepared bus analog control procedures
RISCCPU
- 简单的CPU设计流程PPT，用于教学目的，可综合的verilog HDL设计。-A simple CPU design process PPT, for teaching purposes, can be integrated verilog HDL design.
RS232_PS2_Control
- Verilog语言编写的RS232控制模块以及RS232到PS2的通信接口模块。整个模块已经通过Virtex4的FPGA平台上的硬件仿真和验证。-Verilog HDL model for RS232 and PS2 interface communication control block. It includes the RS232 RX-TX model as well as PS2 model, and it have already been proven in FPGA virtex
fft64
- verilog hdl 编写的64点fft代码，适合很多芯片-coded by verilog hdl that implement 64 point fft, suite to many core
Verilog-HDL--examples
- 王金明：《Verilog HDL 程序设计教程》书中的全部范例，pdf版本。-Wang Jinming: " Verilog HDL Programming Guide" all examples in the book, pdf version.