完整的DDR控制器设计，包含代码、仿真环境、FPGA综合网表等-full DDR controller ip,include rtl code,simulation environment and testbench, fpga synthesis netlist,etc.

4G模块EC20开发资料，硬件设计手册，AT指令，原理图和PCB图封装，完整开发资料。(Development Data of 4G Module EC20 and Hardware Design Manual)