搜索资源列表
8BIT
- 基于FPGA的8位乘法器代码,可以进行四象限乘法
crc7
- CRC计算模块，7位CRC计算。经过FPGA及IC平台验证。-CRC calculation module, 7 CRC calculation. Through the FPGA and IC platform for verification.
20100407
- 用MATLAB仿真的数字下变频程序，变频，滤波未用matlab函数，而是用代码完成，便于移到DSP或FPGA上。供参考。-Using MATLAB simulation of digital down conversion process, conversion, filtering is not used matlab functions, but with code completion, easier to move on a DSP or FPGA. For reference.
matlab
- 《无线通信FPGA实现》这本书中的代码，所有matlab的-" FPGA implementation of wireless communications," the book' s code, all of matlab
cocahome_20100403094552
- 实现基于FPGA的turbo码的编解码matlab代码-FPGA implementation of turbo codes based codec matlab code
FFT
- 自己用Matlab写的FFT的代码，主要是为了FPGA实现的前期建模-FFT using Matlab to write their own code, mainly to preliminary modeling of FPGA implementation
wireless
- 无线通信FPGA设计Matlab Verilog代码-Wireless FPGA design Matlab Verilog code
MPEG2_MAC_Verilog_FPGA
- MPEG2+MAC Verilog代码+文档(FPGA实现)-MPEG2+MAC Verilog code the+ document (FPGA implementation)
Cholesky
- 7阵元Cholesky分解实现代码，FPGA编程的Matlab对应程序，这是一个子函数，使用时对输入矩阵稍加修改即可-7 elements Cholesky decomposition Matlab corresponding program code, FPGA programming, which is a sub-function, use the input matrix can be slightly modified
Display-a-heart-shape-code
- Display a heart shape code点阵显示爱心形的FPGA Verilog 代码-Display a heart shape code
Key-and-digital-tube-display
- 按键和数码管显示，FPGA的verilog代码-Key and digital tube display
Multiplier-digital-tube-display
- 乘法器数码管显示，FPGA的verilog代码-Multiplier digital tube display
Division-of-digital-tube-display
- 除法器数码管显示，FPGA的verilog代码-Division of digital tube display
Adder-digital-tube-display
- 加法器数码管显示，FPGA的verilog代码-Adder digital tube display
matlab-and-fpga-FIR
- 基于MATLAB和FPGA的FIR滤波器的各种资料和程序代码-All kinds of data of the FIR filter based on MATLAB and the FPGA and program code
RISC_CPU_matlab
- RISC处理器的matlab代码，里面每个模块划分都很细致，是 FPGA设计RISC处理器的重要参考-RISC CPU DESIGN
GMSK_BaseBand_Digital_Modulation
- GSM手机信号的基带数字信号调制MATLAB仿真算法，可以直接生成代码载入FPGA板中，这个算法是公司应用过的，肯定可行。请别乱传。 -Baseband digital signal modulation MATLAB simulation algorithm GSM mobile phone signal, you can generate code directly loaded into the FPGA board, the algorithm is applied over the
lzs-master
- 基于verilog的LZS压缩和解压算法，压缩比1；2 。里面带有C原言的代码。已经通过验证！(Verilog based LZS compression and decompression algorithm, compression ratio 1; 2. It has the C code in it. It has been verified!)
数字滤波器的MATLAB与FPGA实现例程代码567
- 数字滤波器的MATLAB与FPGA实现——杜勇(配套光盘) 程序源码，配合电子书使用可以很好的学习数字滤波器的MATLAB与FPGA实现，完整代码，仿真良好，第5、6、7章((MATLAB and FPGA implementation of digital filter -- Du Yong (supporting CD-ROM) program source code, can learn matlab and FPGA implementation of digital filter we
Chapter_9
- 数字滤波器的MATLAB与FPGA实现——杜勇(配套光盘) 程序源码，配合电子书使用可以很好的学习数字滤波器的MATLAB与FPGA实现，完整代码，仿真良好，第9章((MATLAB and FPGA implementation of digital filter -- Du Yong (supporting CD-ROM) program source code, can learn matlab and FPGA implementation of digital filter well w