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16bit-CLA
- a 16 bit carry look ahead adder verilog code
4b_ripple_carry_full_adder
- ripple carry for full adder of 4- bit in verilog
add16
- designing of 16 bit adder using 4 bit adder using verilog code
Adder-digital-tube-display
- 加法器数码管显示，FPGA的verilog代码-Adder digital tube display
day5_fastadder
- this is an implementation of fast adder algorithm in verilog.
MATLAB-and-Verilog-codes
- there are 5 files. the first two codes are written in Matlab as m-files in control system design to show step responses. in contrast, the final three codes are written in verilog ( Quartus II) used in Altera one of them for BCD adder and the other fo
adder
- adder for verilog for complex addition etc