搜索资源列表
7778
- USB接口虚拟仪器之频率计 -USB port of the frequency meter virtual instrument Virtual Instruments USB port of the frequency counter
jishuqivhdl
- 使用 VHDL 描述计数器的设计、综合、仿真的全过程,能够实现多重功能-Counter design using the VHDL descr iption, synthesis, simulation of the whole process to achieve multi-functionality
Shiftpcb
- Proteus VSM includes a number of virtual instruments including an Oscilloscope, Logic Analyser, Function Generator, Pattern Generator, Counter Timer and Virtual Terminal as well as simple voltmeters and ammeters.
Shiftpcb
- Proteus VSM includes a number of virtual instruments including an Oscilloscope, Logic Analyser, Function Generator, Pattern Generator, Counter Timer and Virtual Terminal as well as simple voltmeters and ammeters.
bestsave
- Proteus VSM includes a number of virtual instruments including an Oscilloscope, Logic Analyser, Function Generator, Pattern Generator, Counter Timer and Virtual Terminal as well as simple voltmeters and ammeters.
vhdl
- 使用 VHDL 描述计数器的设计、综合、仿真的全过程,很好用-Counter design using the VHDL descr iption, synthesis, simulation of the whole process, very good use
Counter
- 计数器功能的实现 有前后台的制作 数据库 很容易移植-Counter function before and after the realization of a production database platform is easy to transplant
RTI_example
- RTI模块,实时性计数器模块例程;好代码共享。-RTI module, real-time counter module routines good code-sharing.
frequency-counter
- 这是用verilog写的配合DE2 FPGA开发板的10进制显示频率计的工程文件夹的压缩包,解压后可直接下载到DE2板上,其中频率输入端是系统自带27M时钟D13用于测试,如果想要应用于别的开发板,可以重新分配引脚。-DE2 FPGA development board with with verilog write with decimal display frequency meter project folder compression package, after decompressi
NAR
- CSOL重要文件解压工具 解压文件到X:/Counter-Strike Online/Data 双击运行NARTool.exe 耐心等待-CSOL important file decompression tool unzip the file to a X:\/Counter-Strike Online\/DataDouble click the run NARTool.exe wait patiently...
sine
- 正弦信号发生器的设计,正弦信号发生器的结构由3 部分组成。数据计数器或地址发生器、数据ROM 和D/A。性能良好的正弦信号发生器的设计要求此3 部分具有高速性能,且数据ROM 在高速条件下,占用最少的逻辑资源,设计流程最便捷,波形数据获最方便。下图是此信号发生器结构图,顶层文件SINGT.VHD 在FPGA 中实现,包含2 个部分:ROM 的地址信号发生器,由5 位计数器担任,和正弦数据ROM,拒此,ROM由LPM_ROM模块构成能达到最优设计,LPM_ROM底层是FPGA中的EAB或ESB等。
counter
- implementation of a four bit counter in verilog
wenjianjieyaheduxie
- java实现文件读写和解压 private static void testInput() { // D盘下有个Welcome.java文件,现在按字节读入: int a = 0 // int counter=0 FileInputStream f11 // 输入流 try {-import java.io.BufferedReader import java.io.BufferedWriter import java.io.File
TEXT
- 本设计利用STC89C51单片机的定时器/计数器定时和计数的原理,使其能精确计时。利用中断系统使其能实现开始暂停的功能。根据要求知道秒表设计主要实现的功能是计时和显示。因此设置了三个按键和LED显示时间,三个按键分别是开始、停止和复位按键。利用这三个建来实现秒表的全部功能,而LED则能显示最多59.99秒的计时。-This design uses STC89C51 microcontroller timer/counter timer counting principle and that it
timecounter
- 本设计可直接用作时钟计数器,同时有调时,定时功能。 Led[3:0]显示秒钟的变化情况。 func用作计时,调时,定时功能转换。 Ledarrive用于提示计时时间已到。 change可使秒钟在数码管显示。 plus键在调时计时时使时钟加一。 shift用于调时计时时分计时与时计时的调整转换。-This design can be used directly as a clock counter, while when adjusted, timing function.