搜索资源列表
wierlesscommunicationfpgadesignmatlabverilogcode.r
- 无线通信FPGA设计的所有源码，具有良好的使用价值-verilog matlab ISE
counter
- 本例源代码文件由用户按照书中的操作步骤自己生成，“Example-2-1\Project_Navigator_Demo\源代码”目录下为源代码的参考文件。“Example-2-1\Project_Navigator_Demo\counter”目录下为完整的工程，包括源代码文件、综合与实现的结果文件、ISE工程文件等，可以使用ISE工程管理器打开工程，供读者参考-In this case the source code files by the user in accordance with th
ISE
- 基于ISE软件的使用说明,一看就会使用这个软件-ISE software-based instructions, a look will be using this software
GA
- optimal pid control design for a plant using GA. Here ISE is taken as objective function
ISE_error
- ISE一些常见错误的描述，以及相关的解决办法-ISE WARNING and ERROR common and its solutionISE for some typical mistakes in parsing
system_generator
- 其中详细的介绍了matlab中的simulink仿真时ise联合仿真时所用到的system generator的用法，对做fpga很有帮助哦-Described in detail the usage of the system generator used in the joint simulation in matlab simulink simulation ise to do fpga helpful.
comptage-sur-un-afficheur33
- matbal file for xilinx design ISE ...compteur, bascule-matbal file for xilinx design ISE ...compteur, bascule....
simulink-QPSK
- 对QPSK解调系统完美建模，其中通过改变码元速率和载波频率，再计算相应的环路滤波器的参数，即可实现多种QPSK模型的解调，且该模型可通过SYSTEM generator进行量化，从而生成ISE能直接使用的HDL代码。 matlab版本：2007a-Perfect for QPSK demodulation system modeling, which by changing the symbol rate and carrier frequency, and then calculate t
simulink-8PSK
- 对8PSK完美建模，其中通过改变码元速率和载波频率，再计算相应的环路滤波器的参数，即可实现多种QPSK模型的解调，且该模型可通过SYSTEM generator进行量化，从而生成ISE能直接使用的HDL代码。-Perfect modeling of 8PSK, wherein by changing the symbol rate and carrier frequency, and calculate the corresponding parameters of the loop filte
entrn1
- This paper deals with the various aspects of AGC of interconnected multi-area hydrothermal systems. Thermal area is considered with reheat turbine and hydro area is considered either with an electric governor or a mechanical governor. Optimiza
trp_212
- This paper deals with the various aspects of AGC of interconnected multi-area hydrothermal systems. Thermal area is considered with reheat turbine and hydro area is considered either with an electric governor or a mechanical governor. Optimiza
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
E4_8_FirParallel
- 无线通信系统FIR MATLAB生成模块。ISE完整工程。 -Parallel FIR MATLAB module for wireless telecom system.ISE full project.
scan-alpha-using-nilt-fitting
- Fitting real world data using the fractional order LTI model K/(tau*s^alpha+1)*exp(-Ls). The parameters for fitting are [K,tau,alpha,L]. The code is to automatically sweep the orders with a user specified step size. Error is uated by IAE(integral abs
data_generating
- 用matlab生成的ram数据，可以供给ISE调用的ram.这里产生的是调频连续波的数据程序。-Matlab data generated by ram, ram ISE call can be supplied where the data generated by the program is frequency modulated continuous wave.
puhua_runga
- 用MATLAB实现遗传算法程序，并求使控制性能ISE最小的比例增益Kp,积分时间Ti,微分时间Td的三个参数大小的m文件-Using MATLAB genetic algorithm to achieve the program, and to make the control performance of ISE minimum proportion gain Kp, integral time Ti, differential time m of the three parameters o
absejifenph
- 用MATLAB实现求一阶时滞PID控制的ISE指标并绘图的程序，为m文件-Using MATLAB to achieve the first order delay PID control of the ISE indicators and drawing procedures for the m file