搜索资源列表
13lab03
- 一组开发基于XILINX FPGA开发DSP算法的应用资料，具有实用性，可操作性。（3）-a group Xilinx FPGA-based DSP algorithm development of the information is useful, operability. (3)
Xilinx-FPGA-Matlab-Simulate
- Xilinx-FPGA-Matlab-Simulate.rar
xapp569
- DDC_DUC Xilinx CDMA2000 cpri xapp1018_wcdma
HDB3
- HDB3码的编码，图形，功率谱密度。用于通信原理教学等-Code HDB3 coding, graphics, power spectral density. Communication Theory for teaching
filter
- 这是基于MATLAB下的XILINX的FPGA的FIR滤波器的模型设计文件-This is a MATLAB-based FPGA of the XILINX Model of the FIR filter design documents
arithmetic
- 这是xilinx的FPGA实现各种算数运算的全部基于MATLAB的模型文件，包括加减乘除等-This is the xilinx arithmetic FPGA to achieve the full range of MATLAB-based model of documents, including multiplication and division, such as addition and subtraction
ASK-OOK-FSK-BPSK
- MATLAB实现ASK, OOK, FSK, BPSK, QPSK, 8PSK调制源代码-Free Source Code for ASK, OOK, FSK, BPSK, QPSK, 8PSK Digital Modulation in FPGAs Xilinx using system generator (ASK, BPSK, FSK, OOK, QPSK)
XILINX
- not so good BPSK software matlab
sysgen_gs
- Xilinx system generator的上手指南，system generator用于在matlab中使用simulink设计硬件，很方便-guide of system generater by Xilinx
Rocket
- 很好的高速口的设计资料，很好的高速口的设计资料 很好的高速口的设计资料-In design of large-scale access convergence router(hereafter referred to ACR) forwarding engine, the Xilinx Virtex-4 FPGA!s RocketI/O r multi-gigabit transceiver is used to satisfy the need of high speed and st
XilinxFPGADesign1.1
- learn how to use Xilinx FPGA design in ten minutes
IFData_3Carrier_1e5
- Xilinx WCDMA_V5 ddc_virtex5 CPRI IFData_3Carrier_1e5
ddc_v1_sg81_060405
- DDC_DUC Xilinx WCDMA_V4 ddc_v1_sg81_060405
xapp1018_cdma2000
- DDC_DUC Xilinx CDMA2000 CPRI xapp1018_cdma2-DDC_DUC Xilinx CDMA2000 CPRI xapp1018_cdma2000
pc_cfr_v2_0_msim_r2_0
- Xilinx公司pc_cfr IP核的MatLab仿真-matlab simulation model of pc_cfr ip core of xilinx
cdma2k_ddc_12_1
- matlab simulink 开发的CDMA2K DDC数字下变频器和滤波器，使用XILINX FPGA V5系列，并包含DDC每个阶段的输出验证matlab程序，非常实用。-matlab simulink developed CDMA2K DDC digital down converter and filter, using the XILINX FPGA V5 series, and contains the output of each stage of verification DD
makecoe
- matlab生成*.COE文件，用于xilinx公司FPGA内部存储器的初始化文件-matlab generate*. COE file for xilinx FPGA internal memory company initialization file
fir_cic
- 用matlab生成xilinx FIR参数，对其FIR 核进行配置-Matlab generate xilinx FIR parameters to configure their FIR
Gps-receiver-using-xilinx-fpga-and-ti-dsp-in-matl
- Gps receiver using xilinx fpga and ti dsp in matlab
源码 基于XILINX FPGA的ofdm通信系统基带设计
- verilog 源码 基于XILINX FPGA的ofdm通信系统基带设计(Experiment of digital signal processing: parallel filtering experiment code. I hope it will help.)