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dianti
- 基于Verilog的八层电梯设计，能够实现自动化的电梯控制。-Verilog based on the eight-lift designed to automate the elevator control.
newViterbi217
- 基于IEEE802.11n标准,采用verilog语言设计的(2,1,7)卷积码viterbi译码器,支持1/2,2/3,3/4,5/6四种码率的译码,以测试无误-IEEE802.11n standard Verilog language design (2,1,7) convolutional code viterbi decoder support 1/2, 2/3, 3/4, 5/6 four bit rate decoding to test and correct
digital-frequency-counter
- 基于FPGA的数字频率计，verilog hdl编写-digital frequency counter ，using verilog hdl
uvm-1.1d
- uvm 源代码开发，基于此可以实现芯片验证加速和验证充分保证-uvm system verilog based code
example_design
- 基于Xilinx最新的Virtex-7的存储器IP核的使用，verilog语言编写的所有源码。-Based on Xilinx latest Virtex-7 FPGA,all of the MIG IP code sources by Verilog language.