搜索资源列表
crc_verilog
- 用于计算CRC的verilog HDL源码-CRC calculation for the Verilog HDL source
ZBT SRAM
- 用verilog HDL写的操作SRAM的源码-with Verilog HDL write operation SRAM FOSS
manchester
- 用verilog HDL实现曼彻斯特编码的源码-with Manchester Verilog HDL source code
digtalclk
- 用Altera公司的QuartusII编写的电子钟程序，可以下载至开发板，实现一个智能数字钟功能，计时，校时，闹钟，跑表等功能，也可用于学习verilog HDL语言与数字逻辑
RS encoder(Verilog)
- RS编码的源代码使用Verilog在Xinloinx平台-RS coding using the source code in Verilog Xinloinx platform
verilog LDPC encoder
- 码长1536 扩展因子64的 WIMAX的LDPC 编码器，支持5/6,2/3,3/4,3个码率，需要在顶层做参数修改
tb_cordic
- cordic algorithm in verilog
reed
- this the completedocumentation and code about reed solomon logic implemented on fpga in verilog.-this is the completedocumentation and code about reed solomon logic implemented on fpga in verilog.
lcd_my
- 用于驱动12864lcd的Verilog语言-The Verilog language used to drive 12864lcd
Verilog
- 全加器的Verilog 实现代码 寄存器的Verilog 实现代码-Low-pass filter integral part of full-adder and register the Verilog implementation code
sigmadelta_verilog_code
- sigma delta verilog code and testbench for you to do simulation
qpsk_relate
- QPSK解调机设计,采用相关解调,用硬件语言verilog描述-QPSK demodulation machine design, using the relevant demodulation, using the hardware descr iption language verilog
qam_64
- 64QAM调制,采用硬件语言verilog实现,其中调用了DDS的IP核-64QAM modulation, using language verilog hardware implementation, which is called the IP core of the DDS
FPGA
- 《无线通信FPGA设计》一书中例子的Matlab及verilog代码-" Wireless FPGA Design" a book example of Matlab and the verilog code
qpsk_relate
- QPSK相关接收机及匹配接收机的verilog实现-QPSK correlation receiver and matching receiver verilog implementation
pci_23
- this is 1553B encoder logic writen in verilog. is compatible with 1553 DDC
lab8
- my labs on verilog. this is modeling of proccesor core
verilog
- verilog数字系统设计-rtl综合测试平台与验证 书中源码-verilog Digital System Design-rtl test platform verification book source
CRC-Verilog
- crc的verilog程序,希望可以帮到大家-crc of verilog
traffic-light-Verilog
- 交通灯分为X组和Y组，每组包括了2位倒计时数码管和红黄绿三色LED信号灯（每组包括﹢、-两小组，显示内容一样），考虑到应用需求，要求芯片可通过I2C接口连接到上位机，以调节内部控制寄存器,此为Verilog代码，包含led、seg、timer等模块。-Traffic lights are divided into groups X and Y groups, each including two digital countdown yellow-green and red LED lights