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gcl.src.tar
- BOI version of Steiner tree construction, practical and popular for manhattan VLSI routing, generate a Steiner minimum tree for given set of terminals in a layout plane-BOI version of Steiner tree construction, practical and popular for manhattan VLS
buf_tree_pol.tar
- Construct buffered routing tree for VLSI interconnects in a Manhanttan layout plane for a given set of terminals, guarantee polarity of the terminals agree with each other
FengShui.tar
- FengShui: custom ASIC layout placement for gigascale VLSI circuits, for gate array, sea of gate and standard cell designs, scales well into million gate designs-FengShui: custom ASIC layout placement for gigascale VLSI circuits, for gate array, sea
layout_skill
- 在设计版图中调用自动显示十字标尺帮助对齐-Call automatic Phillips ruler to help align the design layout
D1.1.2
- 根据相关固定参数，场景布置参数以及以往信道参数生成新的信道参数-According to the relevant fixed parameters, scene layout parameters and previous channel parameters to generate a new channel parameters
CLTTest
- TI cache优化的一个例子实现，在该系统中，使用了cache布局工具来完成代码的cache优化，用于消除应用的cache miss。-An example of TI cache optimized implementation, in this system, use the cache layout tools to accomplish cache optimized code for the elimination of the application cache miss.