modelsim下仿真通过，用Verilog写的多周期CPU，是计算机组成原理的大作业，供学弟学妹参考。-Under modelsim simulation by using Verilog write multi-cycle CPU, is composed of a large computer operating principle for mentees reference.

verilog设计的5状态多周期mips -multiple cycle mips CPU design of Verilog

多周期CUP用MIPS汇编的实现，包含了测试指令。(Multi cycle CUP with MIPS compilation of the implementation, including the test instructions.)