搜索资源列表
and1
- 用VHDL语言编写的三位二进制的乘法器，其原理是每位相乘后再错位相加-using VHDL prepared by the three binary multipliers, the principle is that each subsequent dislocation multiplication sum
VHDL
- VHDL对各种电路的基本实现，包括乘法器，触发器，加减法器等-VHDL for the basic realization of the various circuits, including multipliers, flip-flops, and other instruments used in addition and subtraction
eda
- 利用vhdl设计fir滤波器，有完整程序， 包含加法器，乘法器。-Design using vhdl fir filter, a complete program, including adders, multipliers.
demo11-mlt1_vhdl
- 乘法器实验,按动S3,S4,S5,S6按键，可以将S3,S4,S5,S6相乘的结果在LED上显示-Multipliers experiments press S3, S4, S5, S6 keys, can be S3, S4, S5, S6 is the result of multiplying the LED display
multi-verilog
- 乘法器。fft。 基2.蝶形运算。旋转因子-Multipliers. fft. Group 2 butterfly. Twiddle factor
lxy
- 一个简单形象的八位乘法器，VHDL语言汇编，在QUARTUS II 环境下运行-A simple image of eight multipliers, VHDL language compilation environment running under QUARTUS II
Ref-exstfir-VHDL-Code
- code for an fir filter of n length order with different multipliers and adders