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VHDL-3fenpindianlu
- 该程序用VHDL硬件描述语言编写而成,已调试通过,程序运行后可实现三分频,这样就用软件设计代替了硬件设计,方便,稳定,不需要硬件调试!-the procedures used VHDL hardware descr iption language, prepared debugging has passed, After running third frequency can be realized, so software designed to replace the hardware de
VHDL.rar
- 16QAM调制器的Verilog HDL程序，可以实现16QAM调制,16QAM modulator Verilog HDL procedures, 16QAM modulation can be achieved
dlx_verilog.rar
- 这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流水线和Verilog的朋友共享。,This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! T
ldcp_verilog
- ldpc verilog 程序 做ldpc硬件实现的可以-ldpc verilog procedures do LDPC hardware implementation can
any_div_freq
- 可以对输入时钟任意分频(整数或小数),带Quartus II 完整项目文件.-Can be arbitrary points on the input clock frequency (integer or decimal), with complete Quartus II project document.
cd
- 一个彩灯循环控制的VHDL程序,功能还可添加.-Cycle control of a lantern VHDL procedures, functions can also be added.
traffic
- 简单的交通灯,功能为红灯,黄灯,绿灯轮流亮,时间多少可以改变-Simple traffic lights, feature a red light, yellow light, green light rotation, how much time can be changed
recognition
- 语音识别的源码可用于语音识别。。。。。语音识别 的源码可用于语音识别-Speech recognition source code can be used for speech recognition. . . . . Speech recognition source code can be used for speech recognition
fen_zu_interlacing
- 一个简单的交织实现程序，可以自己看看，具体功能很简单，如果看不懂的话可以留言哦，欢迎交流哦-Interwoven to achieve a simple procedure, can take a look at the specific function is very simple, If you do not know if can post Oh, welcomed the exchange of Oh
cvery.comdel7535899835
- 学生成绩管理 实现成绩的查询 录入多个公司的JAVA面试试题，供 ·模式识别matlab工具箱,包括SV ·文件类型：Visual FoxPro 人 ·struts2.0得例子,主要是实现s ·一个C#多线程的例子。 ·卡尔曼滤波器matlab源代码。 ·很不错的vhdl学习实例 几十 ·原版的FAT32手册,E文差的同志 ·常见的JAva面试试题，平时可 ·一个小型C语言编译器 -Student performance managem
workhard
- 数字钟 可实现正常计数校准 还有方电台报时功能 四低一高 闹钟功能-Digital clock can be calibrated to achieve a normal count timekeeping function of the radio side there are four low and one high alarm
clock
- 完成数字钟表的功能，可以实现整点报时，闹钟和设置时间-The completion of the functions of digital watches, you can bring the whole point timekeeping, alarm clock and set-up times
clock
- 电子课程设计数字钟的源代码，已在试验箱上实现，定义了管脚。可以调整时间-E-curriculum design digital clock source code has been achieved in the chamber, the definition of a pin. Can adjust the time
Multiplier
- 用VHDL语言仿真乘法器设计。能够实现一般乘法运算。-Multiplier using VHDL language design simulation. Multiplication can be achieved in general.
spi_Master
- 实现了对SD卡的SPI方式下读写操作，已经测试了，可以直接用-The realization of the SD card to read and write SPI operation mode has been tested, can be directly used
jifenqi
- 主要介绍各类数字积分器的设计。可以有助于你对数字计分器的设计-Introduces the various types of digital integrator design. Can help you on the number of design points
ADDER
- 本设计是用32位的并行全加器的,可以实现浮点运算!-The design is a parallel 32-bit full adder, and floating-point operations can be achieved!
USBverilog
- verilog USB程序，经过实践调试，并且都能成功实现-verilog USB procedures, debugging practice, and can be successfully achieved
EP1C3_81_SCHK
- 序列检测器设计 这里面是一个完整的工程可以直接适用-Sequence detector design there is a complete project can be applied directly
Chapter1-5
- 第一章到第五章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例