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turbo_VHDL
- Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * M
VHDL3-8
- 用VHDL设计的3-8译码器，精简~！-design using VHDL 3-8 decoder, streamlining ~!
sdgshjd
- 数字系统设计这是有关的相关源代码，有简易CPU 除法器、计数器等 ...[fpdiv_vhdl.rar] - 四位除法器的vhdl源程序 [vhdl范例.rar] - 最高优先级编码器8位相等比较器 三人表决器（三种不同的描述方式） 加法器描述 8位总线收发器：74245 （注2） 地址译码（for m68008） 多路选择器（使 BR> ... -Digital System Design This is the underlying source code, a simple C
vhdl
- 3vhdl简单程序设计；4,8-3优先编码器5,3-8译码器；6,6d锁存器；7，数码管扫描显示；8，四位二进制加法计数器-3vhdl simple programming 4,8-3 5,3-8 priority encoder decoder 6,6 d latch 7, the digital scan 8, four binary up counter
HammingDecoder
- -- Hamming Decoder -- This Hamming decoder accepts an 8-bit Hamming code (produced by the encoder above) and performs single error correction and double error detection. -- download from: www.pld.com.cn & www.fpga.com.cn LIBRARY ieee U
control
- 四位微程序控制器的指令译码器，运用VHDL语言实现。-Four micro-program controller instruction decoder using VHDL language.
decoder
- 并行数据向串行数据的转换，实现并到串之间的随意变换-parelell to seriel
t4
- Explain the very good teaching Ve failed to translate miller overall lack of success of verilog language miller decoding Miller verilog language decoder o 4 Multiplier VHDL language design DRAM Controller verilog file
16b20b_Decoder
- VHDL实现的16B/20B解码器。包含两个8B/10B解码器。采用级联方式实现-VHDL implementation 16B/20B decoder. Contains two 8B/10B decoder. Be achieved by cascading
VHDL
- 74LS161 JK触发器带清0端,项目名称为dff_JK_111 十进制计数器74LS290,项目名定为CTLS290：运算方法编写的290计数器：另一种编法LS290 不带使能端的3线8线译码器 八选一数具选择器：用CASE语句 全加器： 简单的JK触发器-74LS161 JK flip-flop with cleared end Project Name dff_JK_111 decade counter 74LS290 project name as CTLS290: and comp
bluespec-reedsolomon_latest.tar
- Reed Solomon decoder implemented in VHDL/Verilog. Includes ASM s
BCH
- 此代码用VHDL实现BCH(57,44,6)编码器，属于信道编码的内容，此外采用Miggitt译码器实现译码功能。-This code BCH (57,44,6) encoder using VHDL, is a channel coding content, the addition Miggitt decoder decoding function.
decode3_8
- 3-8译码器 将数电中3-8译码器用VHDL语言实现 并进行仿真-3-8 decoder, the number of electrical 3-8 decoder applications VHDL language and simulated
VHDL
- seven segment decoder and Counter Program (10 hex)
DEC
- Decoder VHDL test on Digilend Basis2
VHDL
- 3-8译码器 4-2优先编码器 4选1多路选择器-3-8 4-2 priority encoder decoder 4-to-1 multiplexer
vhdl
- 译码器设计 实现3-8译码器的门级和行为级设计；完成3-8译码器的门级和行为级设计的仿真，并下载到开发板进行验证。 用拨挡开关K1，K2，K3作为输入的三位二进制码，输出的8位码分别用LED1~LED8 显示-Achieve 3-8 decoder gate-level and behavioral level design complete the 3-8 decoder gate-level simulation and behavioral level design, and d
tpc_decode_vhdl
- 基于VHDL的TPC译码器的设计，简述了tpc译码的算法步骤，tpc硬件实现的模块和部分vhdl程序-TPC decoder VHDL-based design, outlines the decoding algorithm steps tpc, tpc hardware modules and some vhdl program
decoder
- decoder code vhdl decoder code vhdl