搜索资源列表
HammingDecoder
- -- Hamming Decoder -- This Hamming decoder accepts an 8-bit Hamming code (produced by the encoder above) and performs single error correction and double error detection. -- download from: www.pld.com.cn & www.fpga.com.cn LIBRARY ieee U
Cvolatile
- eee.std_logic_arith.all use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all entity PL_auto1 is port ( clk:in std_logic --系统时钟 set,get,sel,finish: in std_logic --设定、买、选择、完成信号 coin0,coin1: in std_logic --5角硬币、1元硬币 price,quan
sy1
- 28M分频器 D触发器 jk触发器 library ieee -library ieee use ieee.std_logic_1164.all use ieee.std_logic_arith.all use ieee.std_logic_unsigned.all entity ymq is port(num:in std_logic_vector(3 downto 0) dout:out std_logic_vect
sy4
- D74LS74 JK74ls112. LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY D74LS74 is port(clk,clr,PRE,D:in std_logic QT,QTN:out std_logic) end ENTITY D74LS74 architecture bhv of D74LS74 is signal q,qn:std_logic signal x:std_logic
std_logic_1164
- std_logic_1164 package
SPI-Core_nguyen
- SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE
LIBRARY-IEEE
- 加法计数器的设计 任意进制的计数器设计-LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY sun IS PORT(ENA,CLK_IN,CLR:IN STD_LOGIC Y:OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ) END sun ARCHITECTURE A OF sun IS SIGNAL CLK:STD_LOGIC SIGNAL TEMP:INTEG
modulation
- 基于FPGA的QPSK调制library ieee use ieee.std_logic_1164.all -FPGA QPSK modulation