这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流水线和Verilog的朋友共享。,This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! T

一个流水线设计提高FPGA运行主频的实例-a pipeline demo for FPGA written with verilog

用system verilog 来实习的 1 stage pipeline calculator. It has been successful compiled in Modelsim-System Verilog Calculator