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program
- 设计实现4bit FIFO, 数据深度为8， 产生满， 空状态标志-The diagram of FIFO is shown in figure 1. The FIFO consists of two component: FIFO control logic and RAM. The control logic generates the address (ADD) and write enable (WE) to the RAM so that the fi
QPSK_modulator_demodulator
- Wireless_Communication_FPGA设计代码之一：QPSK调制解调的FPGA实现 将相应的源文件复制到本地硬盘上，修改属性为可写，然后在ISE环境中新建工程，然后添加相应的源文件即可。-Wireless_Communication_FPGA one of the design code: QPSK modulation and demodulation of the FPGA to achieve the corresponding source files to loc
5744114893829
- 用VHDL实现16位的简单CPU。具有加减乘除等功能-vhdl cpu can do add sub and so on
add
- 单片机vhdl设计的加法器 运行的芯片为PIC208-adder
VHDL模块
- 直接用模块就行了，加入到quartus里面即可(just use these modularities,then add these into your quartus)