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- 多功能数字钟，、在quartus 2环境中编译通过； 4、仿真通过并得到正确的波形； 5、给出相应的设计报告 -Multifunction digital clock, in the quartus 2 compiler environment through 4, simulation through and get the correct waveform 5, gives the design report
sync_vhdl
- 产生复合同步信号波形，可适用QUARTUS来运行并查看波形-Generate composite sync signal waveform, the applicable Quartus to run and view the waveform
sinput
- 在matalab上建立sin函数完成一个数据库，放入quartus中建立ip核，对其进行仿真-Sin in matalab function to complete the establishment of a database to create quartus Add ip nuclear, its simulation
registers
- 通用寄存器的VHDL代码，可以在quartus实现-General-purpose registers
lxy
- 一个简单形象的八位乘法器，VHDL语言汇编，在QUARTUS II 环境下运行-A simple image of eight multipliers, VHDL language compilation environment running under QUARTUS II
6c39b755f84775a3d8da072f766399e0
- 本文为数字时钟的设计介绍，具体说明如何使用QuartusⅡ软件设计一个基于EP1C6Q240C8芯片的数字钟。该数字钟具备以下功能：1.正常计时2.校正时间3.闹铃设置4.整点报时。-This paper describes the design of a digital clock, specifying how to use the software to design a QuartusⅡ EP1C6Q240C8 chips based on the digital clock. The
vftvdr
- 基于FPGA的DDS信号发生器设计，包含Quartus 的工程，打开即可使用，Verilog 语言编写！-The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language! 朗读 显示对应的拉丁字符的拼音 字典- 查看字典详细内容-FPGA design, including the Quartus project, open to use, Ve
VHDL模块
- 直接用模块就行了，加入到quartus里面即可(just use these modularities,then add these into your quartus)