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VHDL3-8
- 用VHDL设计的3-8译码器,精简~!-design using VHDL 3-8 decoder, streamlining ~!
VHDL
- 74LS161 JK触发器带清0端,项目名称为dff_JK_111 十进制计数器74LS290,项目名定为CTLS290:运算方法编写的290计数器:另一种编法LS290 不带使能端的3线8线译码器 八选一数具选择器:用CASE语句 全加器: 简单的JK触发器-74LS161 JK flip-flop with cleared end Project Name dff_JK_111 decade counter 74LS290 project name as CTLS290: and comp
bluespec-reedsolomon_latest.tar
- Reed Solomon decoder implemented in VHDL/Verilog. Includes ASM s
decode3_8
- 3-8译码器 将数电中3-8译码器用VHDL语言实现 并进行仿真-3-8 decoder, the number of electrical 3-8 decoder applications VHDL language and simulated
VHDL
- seven segment decoder and Counter Program (10 hex)
DEC
- Decoder VHDL test on Digilend Basis2
VHDL
- 3-8译码器 4-2优先编码器 4选1多路选择器-3-8 4-2 priority encoder decoder 4-to-1 multiplexer
vhdl
- 译码器设计 实现3-8译码器的门级和行为级设计;完成3-8译码器的门级和行为级设计的仿真,并下载到开发板进行验证。 用拨挡开关K1,K2,K3作为输入的三位二进制码,输出的8位码分别用LED1~LED8 显示-Achieve 3-8 decoder gate-level and behavioral level design complete the 3-8 decoder gate-level simulation and behavioral level design, and d