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dlx_verilog.rar
- 这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流水线和Verilog的朋友共享。,This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! T
architecure
- provide LDPC hardware descr iption language CODE
BCH
- 此代码用VHDL实现BCH(57,44,6)编码器，属于信道编码的内容，此外采用Miggitt译码器实现译码功能。-This code BCH (57,44,6) encoder using VHDL, is a channel coding content, the addition Miggitt decoder decoding function.
Counter-VHDL
- it is a VHDL code for the counter.
bin_count
- i m sending hdl code of dm using verilog and vhdl with all blocks contain fft,ifft,scrambler,transmitter,receiver.-i m sending hdl code of ofdm using verilog and vhdl with all blocks contain fft,ifft,scrambler,transmitter,receiver.
miller-input
- 密勒码编译器设计，通过vhdl语言,ke yi haohao kan kan-Miller code compiler design by vhdl language
1
- AHB MASTER vhdl code and rtl schematic. dhasu code he bidu check kl lo bhle hi
FIR_Filter1
- This a 4-TAP FIR Filter. This is a VHDL Code that is written by Dr Pooya Torkzadeh.-This is a 4-TAP FIR Filter. This is a VHDL Code that is written by Dr Pooya Torkzadeh.
Dma
- DMA Controller Code in VHDL
encoder
- VHDL Code for D-Flip Flop & Matching Unit