搜索资源列表
test
- Verilog test file not vhd-Verilog test file not vhd
counter.vhd__
- counter.vhd- counter.vhd
example-vhd
- 周润景的《基于VHDL的FPGA设计》的源代码，十分的实用，欢迎下载-Zhou Runjing of the " VHDL-based FPGA design" of the source code, very useful, welcome to download
i2s_top.vhd
- 用于音频总线I2S信号生成，自己编写，已验证。-audio I2S bus
vga_lib.vhd
- VGA Exercise Code UFL VGA LAB -VGA Exercise Code UFL VGA LAB