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clk_div3
- vhdl语言写的基数分频器，多平台，通过MODESIM仿真-vhdl language to write the base dividers, multi-platform, through simulation MODESIM
fftipcore
- 该程序是vhdl语言编写的fft变换的ip核代码，程序中共包含了36个.vhd文件-that the procedure was prepared by the vhdl language fft transform ip nuclear code CPC procedures contained 36. vhd documents
XHDL4[1].0.40
- 实现VHDL和verilog之间的语言转换，方便程序之间的以致，XHDL版本4.0.40。-Achieved between VHDL and verilog language conversion between programs so easy, XHDL version 4.0.40.
key_scan1
- 用verilog语言描述的键盘扫描程序，用于FPGA芯片以及矩阵键盘的测试。-With verilog language keypad scanning procedure.For the FPGA chip and matrix of the keyboard.
VHDL99examples
- 详细介绍了入门级的99个VHDL源程序，并有程序的详细说明，能够帮助提高VHDL语言的基本功。-Details of the 99 entry-level VHDL source code, as well as a detailed descr iption of procedures to help improve the basic skills VHDL language.
FinalCodelast
- last cordic for immplemantaion of cordic with vhdl language it has testbench
debounce
- 按键消抖程序，用Verilog硬件描述语言编写，实现了按键消抖动作-Buffeting eliminate key procedures, using Verilog hardware descr iption language, the realization of the keys for jitter elimination
COUNT0
- 用VHDL语言编写的一种24位的计数器，带即时锁存功能，带清零、控制功能。已经经过仿真验证。-A 24 bit counter with the VHDL language, with instant latch function, with clear, control function. Has been verified through simulation.
XHDL4.0.40.part2
- vhdl语言--verilog语言 转换 2-vhdl language- verilog language translation 2