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add32
- 32位加法器，可以对32位进行逻辑运算，并且带有测试程序-32-bit adder 32 can perform logical operations, and with the test procedures
csa8
- vhdl code four 4-bit carry select adder
adder
- 这是一个最简单的四位的全加器设计，由两个半加器构成，采用的是VERILOG的算法级和门级描述的。-This is one of the easiest of the four full adder design, consists of two half-adder, the VERILOG algorithm-level and gate-level descr iptions.
GUI_adder
- 采用MATLAB GUI 设计的加法器界面，输入两个数，实现两数相加的功能，适合于刚刚接触的同学。-Using MATLAB GUI interface design adder, enter two numbers, two numbers together to achieve the function, just contact for students.