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risc8
- 经典计算机体系结构RISC8的源代码（Verilog），包括CPU、内存、寄存器等的实现-classic computer architecture RISC8 the source code (Verilog), including CPU, memory, such as the realization Register
VerilogHDL_p2s_s2p
- 在微型计算机系统中, CPU与外部的基本通信方式有两种,一种是并行通信即数据的各位同 时传送,其优点是传输速度较快,但数据有多少位就需要多少条传送线 而串行通信中数据一位一位顺序传 送,能节省传送线. 用Verilog HDL语言实现了串并、并串通信接口之间的转换
mips--cpu
- 本文基于32位 MIPS CPU的体系架构，采用Xilinx ISE 9.1i软件，通过使用Verilog语言编写了32位MIPS单周期和多周期CPU的程序，完成了其逻辑设计并进行了仿真测试。-Based on a 32 MIPS CPU architectures using the Xilinx ISE 9.1i software, write a 32-MIPS, single cycle and multi-cycle CPU program completed its logic de
CPU-implementation-in-verilog
- 用verilogHDL实现CPU各项功能-The implementation of CPU funtions based on verilogHDL
lab-1-ALU-design-with-Verilog-HDL
- cpu设计的运算器部分verilog代码，实验资料，包括原理和代码，在modelsim仿真通过-CPU design arithmetic unit part of the verilog code, experimental data, including the principle and code, through the modelsim simulation
lab-4-cpu-design-with-Verilog-HDL
- 用veriloghdl 编写的cpu代码，modusim仿真通过，包括原理图和代码，以实验报告形式写出-CPU code, written in veriloghdl modusim simulation through, including the principle diagram and code, in the form of a lab report write
CPU
- 基于FPGA控制的ASIC CPU系统设计，全是用VERILOG代码编写，可以做加减乘除运算 -FPGA-based control ASIC CPU system design, all made with VERILOG code writing, arithmetic operations can be done
ECOP-13349069-03
- verilog语言实单周期cpu的设计，已经用ise测试、仿真通过。-verilog single cpu
DCC2010-FPGA-CPU16ASM-DCC
- cpu verilog 16 bits to control radio software