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VerilogHDLshejifengpingqihe32weijishuqi
- 本文件介绍的是用VerilogHDL语言设计分频器和32位计数器.-This paper presents the design using Verilog HDL language Frequency Divider and 32 counters.
fenpinqi
- 《分频器设计》绝对好用的EDA实验程序！已经通过测试。VHDL语言编写-"Frequency Divider" absolutely good for EDA experimental procedure! Already passed the test. VHDL language
dividerfrequency
- 分频器，包括2分频，4分频，8分频，16分频；6分频；20分频-Divider, including two-way, 4-way, 8-way, 16 sub-frequency six-way 20 Crossover
shuzipinluji
- 数字频率计的设计可以分为测量计数和显示。其测量的基本原理是计算一定时间内待测信号的脉冲个数，这就要求由分频器产生标准闸门时间信号，计数器记录脉冲个数，由控制器对闸门信号进行选择，并对计数器使能断进行同步控制。控制器根据闸门信号确定最佳量程。-The design of digital frequency meter can be divided into measurement and display count. The basic principle of its measurement i
frequencydivider
- 计数器和分频器的PDF资料，供大家参考哈。希望对大家有用-Counter and frequency divider of the PDF information for your reference ha. Want to be useful to everyone
DPLL
- 数字锁相环频率合成器的设计,鉴相器、环路滤波器、数控振荡器、反馈分频器-Digital PLL frequency synthesizer, phase detector, loop filter, NCO, feedback divider
134946
- The CS5460A is a highly integrated power measurement solution which combines two Analog-to-digital Converters (ADCs), high-speed power calculation functions, and a serial interface on a single chip. It is designed to accurate
23824648pinlvji
- 1. 测量信号:方波 ； 2. 测量频率范围: 1Hz~9999Hz 3. 显示方式: 4位十进制数显示 4. 时基电路由 555 定时器及分频器组成, 555 振荡器产生脉冲信号,经分频器分频产生的时基信号,其脉冲宽度分别为: 1s, 0.1s 5. 当被测信号的频率超出测量范围时,报警. -Measuring signal: square wave measurement frequency range: 1Hz ~ 9999Hz display: four d
div_clk17
- 手写时中分频，17分频，用状态机写成，之欧诺个两个过程语句简单明了易懂-Handwritten carve frequency divider 17, the state machine languages, the two processes Uno a statement, jianji8e clear and understandable
fec_code
- The Slow Peripherals Clock Group includes the McBSPs, I2C, and the UART. The input clock to this clock group is taken the output of divider 2 (D2). by default, the divider is set to divide its input clock by four, but the divide value can be chan
egprog
- EG8010 is a digital pure sine wave inverter ASIC (Application Specific Integrated Circuit) with complete function of built-in dead time control. It applies to DC-DC-AC two stage power converter system or DC-AC single stage low power frequency tra
clk_divR
- frequency divider into reglable frequence
DDS
- 分频器，利用quartus软件或者modelsim软件对频率进行分频，也可在硬件上观察出对信号的分频-Frequency divider, quartus software or modelsim software is used to analyse the frequency divider, can also be used on hardware to detect the signal frequency division
div1_feng
- 用verilog实现除法的功能，其中可以实现整数的除法，并有小数的表示。(verilog divider function ise fpga frequency)