搜索资源列表
kav7key090507
- 以把直接数字频率合成（DDS）看成这样一种技术，它能用数字值形式的信号控制正弦波的频率。最简单的DDS电路包括一个二进制计数器，一个以等间隔正弦波值进行全波编程的ROM，以及一个数模转换器，用于将存储的正弦波值转换为电压。计数器的时钟频率决定了正弦波的频率，但这种结构并不灵活。 -To the Direct Digital Synthesis (DDS) as such a technology, it can use the digital value of the form of the
Graycodeconvertor
- It is a code for Gray code counter.It can convert normal binary numbers into gray codes
Counter
- 所谓24进制计数器,要在数码管上直观的显示0,1…..22,23等数,再归零-The so-called binary counter 24 to the digital control on the visual display 0,1 ... .. 22,23 and a few, then zero
binary_counter_structural
- binary counter in structural style
8-jinzhi-counter
- 8进制计数器 每计数八次进一次位，vhdl语言的基础程序，对初学者很有帮助-8 binary counter into a bit of each of eight counts, vhdl language based program, very helpful for beginners
10-jinzhi-counter
- 10进制计数器 每计数十次有一个进位，是vhdl编程的基础程序，应用于fpga cpld可编程逻辑器件-Total scores of 10 binary counter has a per carry, is the basis for vhdl programming procedures used in programmable logic devices fpga cpld
18073609
- 利用两片74160制成的24/12进制计数器，可以作为数字钟的一部分-Made use of two 74 160 24/12 binary counter, digital clock can be used as part of
list_ch04_09_free_run_bin_counter
- A free-running binary counter circulates through a binary sequence repeatedly. For example, a 4-bit binary counter counts from "0000", "0001 ", . . ., to " 11 1 1" and wraps around.
mcd-lED2
- 学习《单键触发8位二进制累加计数器》该程序的目的是让大家熟悉输入、输出端口的使用，该程序的功能是把演示板当做一个按键计数器。刚刚接通电源时，8只发光二极管都不亮。表示计数器初值为0，当按下开关S3（RB0）时，计数器的值加1，发光二极管D3点亮，表示值1，然后松开按钮；再次按下开关S3（RB0）时，计数器的值又加1，发光二极管D4点亮，表示值2，依次类推，反复循环。-Learn " Speed trigger 8-bit binary up-counter&q
counter
- 一、基础部分（70 ） 设计一个简易计算器，它具有下列运算功能： 1. 两个无符号的8位二进制数的相加； 2. 两个无符号的8位二进制数的相减； 3. 数值和运算符用4×4键盘输入，输入的值为十进制，其中A为“+”，B为“-”，C为“退格”E为“=”， 4. 数值用数码管以十进制形式显示，以加法为例，初始时显示全“0”，先输入被加数，输入时数字顺序是从左到右。例如，输入1、2、3应该在显示器上上显示“123”，在输入运算符，按下运算符键后，数码管显示全“0”，再输入加数，方法
u3
- 计数器改编成非10进制的。具备置数功能，进位输出功能-Counter adapted into a non-decimal. Have set the number of binary output function
VHDL_design
- 本综合实验包括节拍脉冲发生器、键盘扫描显示和八位二进制计数器三个模块。采用VHDL语言为硬件描述语言，Xilinx ISE 10.1作为开发平台，所开发的程序通过调试运行验证，初步实现了设计目标。-This includes comprehensive experimental beats pulse generator, display and keyboard scan eight binary counter three modules. Using VHDL as the hardwar
counter2
- 带参数的任意进制加减法计数器，同时带有显示功能-With parameters subtraction arbitrary binary counter, and with a display function
cny24
- 24进制加法计数器适用于vhdl和quartus-24 binary adder vhdl counter applied and quartus
DCNT60
- 60进制计数器设计仿真文件，已经经过仿真，程序及仿真结果无误。-60 binary counter design simulation files, has been the simulation program and simulation results are correct.
jishuqi
- 4位二进制的计数器 Verilog 代码-4-bit binary counter Verilog code
getmswpfeat
- matlab vide the examined window into cells (e.g. 16x16 pixels for each cell). For each pixel in a cell, compare the pixel to each of its 8 neighbors (on its left-top, left-middle, left-bottom, right-top, etc.). Follow the pixels along a circle, i.e
SYNCHRONOUS-BINARY-COUNTER
- VHDL (VHSIC Hardware Descr iption Language) is a hardware descr iption language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as