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pinlvji
- 这是一个基于FPGA的频率计和相位计的设计方案-This is an FPGA-based Cymometer and design phase of the program
8bit.详细的八位十六进制频率计课程报告
- 详细的八位十六进制频率计课程报告，是我的eda课程设计报告书,Detailed eight hexadecimal Cymometer curriculum report is my report on the curriculum design EDA
aaa.rar
- EDA基于VHDL语言的数字频率计的设计及其仿真,EDA figure based on the VHDL language Cymometer Design and Simulation
61EDA_D1049
- 频率计设计６位数码管还是拉倒机是大撒但是的撒但是 -6 Cymometer design digital control machine or leave it is spreading
Multi-Function-Digital-Cymometer
- 没用过你说的那种VC3165 智能频率计,27MHz的频率有点高，可以用100M的显波器看，一般的设备搭上去可能会改变频率，要不就拿个接收的试，调到接收器能收的到那就是27MHz了-You say that s the VC3165 intelligence frequency plan, and the frequency of MHz a little high, can use of 100 M show filter is look, general equipment take up
频率计报告正文
- 简易频率计汇编语言计数法包括计数进制转换和显示程序(digital cymometer)