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PLLprogram
- 数字锁相环程序，适合于FM、AM开发 数字锁相环程序，适合于FM、AM开发-DPLL procedures for FM, AM Development DPLL procedures for FM, AM Development
010919.pdf
- 全数字锁相环ＶＨＤＬ描述并实现功能仿真，另附有图形说明-DPLL VHDL descr iption and achieve functional simulation, followed by graphic shows
verilogpll1234
- 基于verilog的全数字锁相环的设计，基于verilog的全数字锁相环的设计。-verilog DPLL the design, verilog based on the DPLL design.
200761311574149479
- 介绍了如何使用数字锁相环,如何用VHDL实现数字锁相环-on how to use the DPLL, how to use VHDL DPLL
DPLL
- 介绍了一宽带的数字锁相环的实现方法，欢迎大家踊跃下载
verilog_dpll_
- 该源代码是用FPGA实现数字锁相环的逻辑，有需要的可以借鉴参考一下。-The source code is to use FPGA implementation of digital phase-locked loop logic, those in need can draw reference.
DPLL5
- 基于FPGA的DPLL的设计打包文件,有详细的描述文件-Design of FPGA-Based DPLL package files
DPLL
- 基于VHDL语言的DPLL电路的设计，给出了设计方案和部分源代码 -DPLL
DPLL
- 数字锁相环频率合成器的设计,鉴相器、环路滤波器、数控振荡器、反馈分频器-Digital PLL frequency synthesizer, phase detector, loop filter, NCO, feedback divider
fm_txrx_simple
- dpll demoudulation in FM
USB1.1-VHDL
- USB PHY RX DPLL This source file may be used and distributed without restriction provided that this copyright statement is not removed from the file and that any derivative work contains the original copyright notice and the associated disclaimer.-US
Matlab-about-pll
- 。在总结前人提出的一些锁相环仿真模型的基础上,用Matlab 语言构建了一种新的适用于全 数字锁相环的仿真模型 对全数字锁相环版图进行了SPICE 仿真,与该模型的仿真结果相验证。-. Built using Matlab language summary of some of the previously proposed phase-locked loop simulation model based on a simulation model of a new applicable t
ADPLL-patent
- 全数字锁相环的几个专利，全部为英文，很好的参考资料-DPLL patent
00258213
- This paper presents a generalized nonlinear (Markov) analysis technique for evaluation of the statistical performance of uniformly sampled digital phase-locked loops (DPLL). Recently proposed synchronization algorithms use more discrete t