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利用QuartusII的"MegaWizard Plug-In Manager",
设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE
把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行
时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。
2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_
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Verilog HDL 在QUARTUS II下的编译和仿真顺序-Verilog HDL in QUARTUS II compiler and simulation under the order of
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FPGA的I2C总线模拟，采用verilog HDL语言编写-I2C bus of the FPGA simulation, verilog HDL language used
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针对DVB-T标准ETSI EN 300 744 V1.5.1,设计了可用于DVB-T接收整机的多速率DDC模块,并在FPGA中仿真实现.在复用数字振荡混频模块的基础上,根据输入信号的不同带宽(6M/8MHz)选择不同的抽取滤波器组完成抽取因子为3或4的多速率处理任务,利用两级半带滤波器(HBF)级联完成4倍抽取滤波,单级奈奎斯特滤波器完成3倍抽取滤波.-For the DVB-T standard ETSI EN 300 744 V1.5.1, designed for DVB-T recei
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介绍一种用于卫星姿态测量的CMOS图像敏感器--STAR250的时序驱动信号，并使用Verilog HDL语言设计驱动时序电路。经布线、仿真、测试后验证了驱动信号的正确性。 -Introduce a measurement for the satellite attitude CMOS image sensor- STAR250 timing drive signals, and use the Verilog HDL language design-driven sequential circ
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仔细讲解了如何在Modelsim中建立Altera的仿真库(Verilog HDL)，如何使用Modelsim建立工程以及代码调试中的注意事项。-Carefully explained how to create Altera simulation Modelsim library, how to use Modelsim to establish engineering and debugging the code in the note.
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Verilog simulation
如何用verilog写Test bench末进行仿真-Verilog simulation
It describe how to write a test bench in veriog for design simulation.
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IEEE 2001 verilog 标准 ,详细讲述了 业内 公认的 VERILOG 标准 ,-The Verilog¤ Hardware Descr iption Language (Verilog HDL) became an IEEE standard in 1995 as IEEE
Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstractio
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Cadence公司的NC-Verilog® Simulator Help文档，内容很全面共1446页。-The Cadence® NC-Verilog® simulator is a Verilog digital logic simulator that combines the
high-performance of native compiled code simulation with the accuracy, fl exibility, and
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本文基于32位 MIPS CPU的体系架构，采用Xilinx ISE 9.1i软件，通过使用Verilog语言编写了32位MIPS单周期和多周期CPU的程序，完成了其逻辑设计并进行了仿真测试。-Based on a 32 MIPS CPU architectures using the Xilinx ISE 9.1i software, write a 32-MIPS, single cycle and multi-cycle CPU program completed its logic de
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cpu设计的运算器部分verilog代码，实验资料，包括原理和代码，在modelsim仿真通过-CPU design arithmetic unit part of the verilog code, experimental data, including the principle and code, through the modelsim simulation
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用verilog 编写的32位存储器代码，modusim仿真通过，包括原理图和代码，以实验报告形式写出-32-bit memory code written in verilog, through modusim simulation, including the principle diagram and code, in the form of a lab report write
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用veriloghdl 编写的控制器代码，modusim仿真通过，包括原理图和代码，以实验报告形式写出-Controller code, written in veriloghdl modusim simulation through, including the principle diagram and code, in the form of a lab report write
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用veriloghdl 编写的cpu代码，modusim仿真通过，包括原理图和代码，以实验报告形式写出-CPU code, written in veriloghdl modusim simulation through, including the principle diagram and code, in the form of a lab report write
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完成通信系统中数据交织器的设计的设计，要求用Verilog HDL编程，包括源程序，仿真波形和实验结果及分析结论等。
-Completed the design of the communication system data interleaver design requirements using Verilog HDL programming, including source code, simulation waveforms and experimental results an
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UART（Universal Asynchronous Receiver Transmitter，通用异步收发器）是广泛使用的异步串行数据通信协议。下面首先介绍UART硬件接口及电平转换电路，分析UART的传输时序并利用Verilog HDL语言进行建模与仿真，最后通过开发板与PC相连进行RS-232通信来测试UART收发器的正确性。-UART (Universal Asynchronous Receiver Transmitter, Universal Asynchronous Receive
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基于cordic算法的DDS的Verilog代码。经过仿真验证，绝对可靠。-Based on cordic algorithm DDS Verilog code. Through the simulation, is absolutely reliable.
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Verilog 程序的学习，Verilog是通信工程专业学生经常使用的一种仿真程序-Verilog program of study, Verilog is a simulation program communication engineering students often use
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Verilog simulations of different project problems.
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vcs的仿真教程，非常详细管用，希望下载(VCs simulation tutorial, very detailed, useful)
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