搜索资源列表
IEEE_Verilog_2001
- Verilog 2001 编程规范，作为ASIC和FPGA逻辑开发人员学习不可多得的资料，也可以作为逻辑开发高手们学习查阅的工具。新手们可以按照实例自己编程操练。
DDS
- 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
iic_master
- it is a iic source verilog code with its testcase which can act only as master
EtherCAT_Communication
- ethercat通讯协议的详细说明及编程提示-ethercat a detailed descr iption of communication protocols and programming tips
mux2x1
- mux 2x1 designed on vhdl fpga adv. pro