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cy7c68013工作在SLAVE FIFO下的FPGA源代码
- cy7c68013工作在SLAVE FIFO下的FPGA源代码，已经通过，Verilog编写,cy7c68013 slave fifo mode code ,written by hard ware language
UART_spec
- a UART model with FIFO buffer, design with verilog
labQ2
- Source codes for verilog fifo for spartan 3
fifo
- this verilog program for sysnchronous FIFO ,this document contains some error using before correct and then use,-this is verilog program for sysnchronous FIFO ,this document contains some error using before correct and then use,
source_code
- verilog code fifo memory usb
FIFO
- FIFO(first in first out) design written in Verilog
syn_fifo
- 基于systemverilog的异步fifo-fifo of design ，system verilog
fifo_module
- verilog 语言写的FIFO历程，可以很好参考。 -The write FIFO verilog language course, a good reference.
FIFO
- FIFO verilog VHDL-FIFO verilog VHDL
fifo
- 这篇文档主要是描述了fifo的作用，里面有用verilog写的源码，及其综合后的结果-This document mainly describes the role of the FIFO inside useful verilog to write source code, and its consolidated results
FIFO-[Compatibility-Mode]
- fifo specification for designing verilog
ht_fifo
- fifo 读写代码，能够进行速率匹配，很好的源代码-verilog hdl
Cy7C68013_SLAVE-FIFO_Verilog
- 针对CY7C68013在SLAVE FIFO 模式下读写Verilog源代码-For CY7C68013 in the SLAVE FIFO mode to read and write Verilog source code