搜索资源列表
ISE
- 是ISE的中文教程，主要是对初学者演示和展示在XILINX的ISE集成软件环境下，如何用VHDL和原理图的方式进行设计输入，用MOdelsim方针。-ISE is a Chinese course is mainly for beginners and display presentation of the ISE in XILINX Integrated Software environment, how to use VHDL and schematic design entry way,
xilinx-fpga
- 详细介绍了 关于xilinx FPGA的内部结构，熟悉内部结构对于编写高效的代码有十分重要的作用-Detailed information on the internal structure of the xilinx FPGA, and is familiar with the internal structure of the code for the efficient preparation of a very important role
opb_ethernetlite
- The Ethernet Lite MAC (Media Access Controller) is designed to incorporate the applicable features described in the IEEE Std. 802.3 Media Independent Interface (MII) specification, which should be used as the definitive specification. Differences bet
xst
- 赛灵思披露本用户手册，手册，发布说明，和/或specifcation（“文档”）于y欧 仅在外观设计dev的elopment使用操作与赛灵思0712的设备。辎欧不得复制， 分发，重新发布，下载，展示，张贴，或传送的文件以任何形式或通过任何方式 包括但不限于电子，机械，影印，录制，或其他未经事先， 赛灵思公司的书面同意。赛灵思发表任何声明，产生的Y我们的文档使用了。 赛灵思reserv展览服务部的自行决定权，变更，恕不另行通知随时文档。赛灵思
dividefreq
- Multiple frequency dividers in VHDL, with comments in Spanish. Is a project done with Xilinx ISE application. It divides 50 MHz in 1, 2, 4 and 8 Hz.
spartan6_fpga_CLB_guide
- xilinx FPGA的CLB高效设计，对提升设计质量很有用-xilinx FPGA' s CLB efficient design, to enhance the quality of design is useful
DDRIO
- Xilinx公司开发板中的一个模块，在时钟的上升和下降沿同时传输数据。使用时需要在ISE集成开发环境下利用VHDL进行例化。本文是对该模块功能的说明，是个人的学习总结-Xilinx has developed a module board, in the clock' s rising and falling at the same time transmission of data. ISE needs to use integrated development environment
Synthesis_and_Simulation_Design_Guide
- xilinx的综合与仿真设计指导书，内容基础，讲解细致，比较可惜的是资料是英文的。-xilinx synthesis and simulation design guide book, the content-based to explain detailed comparison is a pity that the information is in English.
lab1
- 经典嵌入式EDK设计教程，使用的是XILINX公司的EDK开发软件。这是教程的第一部分-Classic embedded EDK design tutorials, using XILINX' s EDK software development. This is the first part of the tutorial
lab2
- 经典嵌入式EDK设计教程，使用的是XILINX公司的EDK开发软件。这是教程的第二部分-Classic embedded EDK design tutorials, using XILINX' s EDK software development. This is the second part of the tutorial
lab3
- 经典嵌入式EDK设计教程，使用的是XILINX公司的EDK开发软件。这是教程的第三部分-Classic embedded EDK design tutorials, using XILINX' s EDK software development. This is the third part of the tutorial
lab4
- 经典嵌入式EDK设计教程，使用的是XILINX公司的EDK开发软件。这是教程的第四部分-Classic embedded EDK design tutorials, using XILINX' s EDK software development. This is the fourth part of the tutorial
lab5
- 经典嵌入式EDK设计教程，使用的是XILINX公司的EDK开发软件。这是教程的第五部分-Classic embedded EDK design tutorials, using XILINX' s EDK software development. This is the fifth part of the tutorial
ppl
- 锁相电路是相位锁定环(Phase Locked Loop)的简称，主要由鉴相器、环路滤波、压控振荡器成 。主要是要掌握LabVIEW图形化编程特点，-PLL circuit is phase-locked loop (Phase Locked Loop) for short, mainly by the phase detector, loop filter, VCO into. Mainly to grasp the features of LabVIEW graphical programm
xilinx
- This documentation of Xilinx course-This is documentation of Xilinx course
xilinx
- 这是xilinx FPGA的学习ppt 里面详细讲解了具体操作及模块的编写方法-This is xilinx FPGA learning ppt which explain in detail the preparation method and module specific operations
Xilinx
- 使用Xilinx的FPGA开发教程，Xilinx平台主要支持VHDL和Verilog的编程和实现。-Using Xilinx FPGA development tutorial, Xilinx platform is mainly supported by the programming and implementation of VHDL and Verilog.
face-recogn.--in-xilinx-EDK
- it is a approach for implementing face recognition using xilinx EDK .
Xilinx 6 Family2
- and blogs ask visitors to register before they can view content, post comments or download something. Temp-Mail - is most advanced throwaway email service that helps you avoid spam and stay safe.
pg137-axi-usb2-device(xilinx USB ip core)
- xilinx USB ip 核使用说明文档，接口完全和usb3320接口一致(Xilinx USB IP core usage instructions document, the interface is completely consistent with the usb3320 interface)