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JTAGrep
- OPEN-JTAG ARM JTAG 測試原理 1 前言 本篇報告主要介紹ARM JTAG測試的基本原理。基本的內容包括了TAP (TEST ACCESS PORT) 和BOUNDARY-SCAN ARCHITECTURE的介紹,在此基礎上,結合ARM7TDMI詳細介紹了的JTAG測試原理。 2 IEEE Standard 1149.1 - Test Access Port and Boundary-Scan Architecture 從IEEE的JTAG測試標準開始,JTA
ARM_JTAG_debug
- 主要介绍ARM JTAG调试的基本原理。基本的内容包括了TAP (TEST ACCESS PORT) 和BOUNDARY-SCAN ARCHITECTURE的介绍,在此基础上,结合ARM7TDMI详细 介绍了的JTAG调试原理。-ARM JTAG debugger introduces the basic principles. Basic elements include TAP (TEST ACCESS PORT) and BOUNDARY-SCAN ARCHITECTURE in
Mixed-Boundelopment
- 数模混合边界扫描技术的研究现状与进展Mixed-Boundary-Scan Technology Research and Development-Mixed-Boundary-Scan Technology Research and Development
Advanced_Trace32_Features
- 先进的trace32特性: 如果您已经对Lauterbach工具比较熟悉, 但是您仍然觉得有些问题,你无法通过Lauterbach工具解决, 不妨可以了解一下该文档中提到的功能。例如: 协议分析, 边界扫描等。-Advanced trace32 features: If you have Lauterbach tools are more familiar with, but you still feel a little problem, you can not be resolved by