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smdk2416_rev0_1_cpu_ddr2_080529
- 三星新的ARM9 S3C2416的电路图纸，可支持DDR2,MLC FLASH-Samsung ARM9 S3C2416 new circuit drawings, supports DDR2, MLC FLASH
DDR_Eye_Patterns
- DDR1 DDR2 DDR3眼图分析。本文根据自己设计的DDR“读”“写”分离软件，介绍一种把“读”眼图和“写”眼 图分离开的方法，并创新地引入模板测试的方法。-DDR1 DDR2 DDR3 Eye Patterns
byNeyno_
- micron data sheet for designing the ddr2 sdram controller part1
DDR
- 关于DDR SDRAM的详细原理和时序分析,对于开发设计有很大使用价值-DDR SDRAM on detailed principles and timing analysis, design for the development of a great value
fpga-pinball_for_c
- VHDL 基于FPGA 和VGA 接口的应用设计-vhdl
DDR2_hardcore_userguide
- xillinx Spartan6 FPGA DDR 接口设计指南-xillinx Spartan6 FPGA DDR Interface Design Guidelines
EFL50-LS2766P-VGA-DDR2-R10-20051222
- Compal Mini (EFL50) ATI VGA/B M52-P
S5PC100_UM_REV1.04
- Samsung s new ARM cpu datasheet. S5PC100 Spec. - CPU ARM Cortex-A8 667-833Mhz - 32KB L1, 256KB L2 Cache - Video 720p (1280x720 Play. h.264 divx, mp4...) - nand, sd/mmc, usb booting - Windows CE 6.0, Linux (*Android) support - support 1
Au1300_B_20090210
- RMI s Au13xx CPU Datasheet. CPU Spec. - MIPS CPU 533,667,800MHz - Video 1280x720 play (Au1370, Au1380) - support memory bus clock 333MHz (DDR2-667) - simular to Au1250-RMI s Au13xx CPU Datasheet. CPU Spec. - MIPS CPU 533,667,800MHz -
DDR2deFPGAsheji
- 使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器以及DDR2 SDRAM操作时序-Using the Virtex-4 FPGA devices to achieve DDR SDRAM and DDR2 SDRAM controller operation timing
ml505_mig_design_creation
- 关于ddr2设计的很好的材料，关于ddr2设计的很好的材料-Ddr2 design on a good material, good design on the material ddr2
sdram_introduce
- sdram内存技术指南（sdr,ddr,ddr2,ddr3）-sdram memory technology guide (sdr, ddr, ddr2, ddr3)
MT47H128M4_MT47H64M8_MT47H32M16
- micron公司DDR2 SDRAM资料：MT47H128M4_MT47H64M8_MT47H32M16.pdf-micron DDR2 SDRAM：MT47H128M4_MT47H64M8_MT47H32M16.pdf
TMS320DM646x--DDR2-Controller-
- TMS320DM646x DDR2 Memory DDR2控制器指导说明-TMS320DM646x DMSoC DDR2 Memory Controller User s Guide (Rev. C)(sprueq4c).rar
childers
- micron data sheet for designing the ddr2 sdram controller part2
DDR2standardize-Chinese-version
- DDR2规范中文版，对ddr2控制器编写十分有用-DDR2 specification Chinese version prepared ddr2 controller is very useful
ddr2
- DDR2 pcb布线规则,BGA布线应该注意-DDR2 pcb routing rules, BGA wiring should be noted
DDR2-User-Interface-PPT
- design of DDR2 with Xilinx
DDR2-controller
- My package named design DDR2 Synchronous Data Random Access Memory by verilog.The memory controller is a digital circuit which manages the flow of data going to and from the computer s main memory. It can be a separate chip or integrated into another
DDR
- 低功耗DDR3芯片手册,DDR2芯片手册(Low power DDR3 chip Handbook,DDR2 chip Handbook)