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svc
- svc，静态电压补偿器，属于一个典型的电压稳定程序，pscad模型-it is svc,uesd for the compentation of voltage,it is a starded model of stability of voltage.
verilog-a-lrm-1-0
- The information contained in this draft manual represents the definition of the Verilog-A hardware descr iption language as proposed by OVI (Analog TSC) as of January, 1996. Open Verilog International makes no warranties whatsoever with respect t