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8254Verilog
- 用Verilog语言编写程序，基于FPGA实现设计8254的相关电子文件-With the Verilog programming language, based on FPGA to achieve the relevant electronic document design 8254
source_code
- verilog code fifo memory usb
FIFO
- FIFO(first in first out) design written in Verilog
Verilog
- 关于VERILOG语言的设计的中文说明书，对于初学者很有帮助，建议看一看-VERILOG language on the design of the Chinese instructions, very helpful for beginners, it is recommended to see
DDRcontroller
- 对DDR控制器的FPGA实现及其代码和参考注释-verilog source code written to read and write DDR
VGA
- VGA presnt of my friend in verilog-VGA presnt of my friend in verilog.....
DAC
- 主要实现对DA转换器的控制、调试程序，使用Verilog语言实现其功能-Main achieved control of the DA converter, debugger, use the Verilog language function
Verilog_xl
- Verilog—xl很全的设计文档，能帮助在短时间内学会Verilog—xl-Verilog-xl is full of design documents, can help immediately learn Verilog-xl
FIR
- FIR filter using verilog code
FPGAdeguangshanjiancejishu
- 本文档设计了1光栅位移传感器信号的接收、光栅位移传感器信号的整形及电平转换电路设计，用Verilog HDL描述了锁相倍频细分和零位信号处理电路。利用FPGA实现光栅位移系统与上位机接口的电路原理框图-This document designed a grating displacement sensor signal reception, grating displacement sensor signal shaping and level conversion circuit design
Watch
- Design Watch with set time by Verilog for kit DE2
fft_fpga
- FFT（快速傅里叶变化）蝶形算法 Verilog HDL语言-FFT Verilog HDL
ram_top
- arm ahb slave bus sram ip in verilog
verilog-basics
- basic design and coding for verilog hardware descr iption language
syn_fifo
- 基于systemverilog的异步fifo-fifo of design ，system verilog
FPGA--uart(verilog)
- verilog uart 源码，编译器ISE9.1i版本，很有用的源码-verilog uart code
verilog
- verilog程序实例，各种简单程序，实用于多数初学者-verilog examples of procedures that a variety of simple procedures, practical for most beginners
Verilog-IEEE-Std(1364-2005)
- Verilog IEEE Std(1364-2005) 标准,硬件开发必备手册-Verilog IEEE Std (1364-2005) standards, hardware development of the necessary manual
Verilog
- verilog学习书籍，很容易上手 希望大家能够喜欢-verilog study book，it is easy to study, hope who will happy
A-Verilog-HDL-Test-Bench-Primer
- 学习资料：详细说明了如何用Verilog语言编写Testbench文件-Learning materials: detailed descr iption of how to use Verilog language Testbench file