利用verilog语言，从上至下层次管理的设计思想；Verilog HDL的行为描述和结构描述,实现8位频率计，4个0检测修正电路的原理说明-The use of Verilog language, top-down hierarchical management design idea Verilog HDL descr iption of the behavior and structure of a descr iption of the realization of frequency

这是一个利用verilog HDL语言编写的自动频率计设计项目，能运行-This is a verilog HDL language automatic frequency meter design projects, and be able to run

基于verilog HDL的频率计设计，多个模块，误差较小。-Based on the the verilog HDL frequency meter design, multiple modules, the error is smaller.

这是基于fpga设计的数字频率计每个模块的 verilog hdl-This is based on verilog hdl fpga design of digital frequency meter for each module