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compensationfilterdesign
- 带余弦预滤波和补偿滤波的抽取滤波器 设计方案-Pre-filtering with a cosine decimation filter and compensation filter design
FPGAfir
- FPGA实现FIR抽取滤波器的设计 采用基于分布式思想的方法来设计FIR滤波器。-FPGA realization of FIR decimation filter design ideas based on a distributed approach to design FIR filters.
lvbofangfa
- 针对全数字软件接收机中抽取滤波器的设计,提出了一种适合在FPGA内实现的单级积分清洗的滤波器结构,这种结构解决了传统积分梳妆滤波器中可能出现的积分器溢出问题,同时还可进行非整数倍的抽取变换.给出了一种无乘法半带滤波器的IIR实现结构,并对该滤波器性能进行了仿真,结果表明在输出过采样率大于4时基本不会影响系统误码性能.-Software for all-digital receiver decimation filter design, presents a suitable FPGA integ
DDCFPGA
- 针对DVB-T标准ETSI EN 300 744 V1.5.1,设计了可用于DVB-T接收整机的多速率DDC模块,并在FPGA中仿真实现.在复用数字振荡混频模块的基础上,根据输入信号的不同带宽(6M/8MHz)选择不同的抽取滤波器组完成抽取因子为3或4的多速率处理任务,利用两级半带滤波器(HBF)级联完成4倍抽取滤波,单级奈奎斯特滤波器完成3倍抽取滤波.-For the DVB-T standard ETSI EN 300 744 V1.5.1, designed for DVB-T recei
fujian
- ：抽取是软件无线电中最核心部分。通过对多项抽取结构的分析，设计出一种多 级抽取滤波器的实现方案，并通过MATLAB仿真实现。 关键词：软件无线电；多相结构；多级抽取滤波器-: Extraction is the most central part of the software radio. By taking a number of structural analysis, design a multi-stage decimation filter implementation sc
cic
- 有关于cic抽取滤波器的FPGA分析研究和实现-Decimation filter on the FPGA cic Analysis and Implementation
radix2
- fft The radix-2 algorithms are the simplest FFT algorithms. The decimation-in-time (DIT) radix-2 FFT recursively partitions a DFT into two half-length DFTs of the even-indexed and odd-indexed time samples. The outputs of these shorter FFTs ar
CIC_Decimator_2stages
- --Filename: gh_CIC_decimation_m1.vhd -- --Descr iption: --CIC Decimation Filter m = 1. -- --Copyright (c) 2005, 2006 by George Huber --an OpenCores.org Project --free to use, but see documentation for conditions -- -- Revision
pudn
- The program is about designing chebychev digital filter,butterworth filter,decimation program