设计了一个双精度浮点乘法器。该器件采用改进的BOO TH 算法产生部分积, 用阵列和 树的混合结构实现对部分积的相加, 同时, 还采用了快速的四舍五入算法, 以提高乘法器的性能。把 设计的乘法器分为4 级流水线, 用FPGA 进行了仿真验证, 结果正确 并对FPGA 实现的时序结果 进行了分析。-Designed a double-precision floating-point multiplier. The device uses an improved algorithm fo

迭代接收机设计方案，包括数字通信简介，Marginals and the sum–product算法等-iterative receiver design

VHDL stands for VHSIC (very high speed integrated circuit) HDL From Boolean algebra, we know that each row of a truth table represents a product term and the output can be written as the sum-of-products expression-VHDL stands for VHSIC (very high spe