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LTE-xilinx_PFGA_reference_design_all
- xilinx中一整套关于LTE在FPGA下的解决方案，里面涉及到LTE设计的L1层和L2层以及结合其硬件的设计方案和内容，非常利于LTE开发-xilinx set on the LTE solution under the FPGA, which relates to the design of LTE L1 and L2 layers and the combination of the hardware design and content development is beneficial
vga_block2
- 一个xilinx工程，自己做的，主要是在VGA上显示一个动态方块，在屏幕上自由移动，碰壁反弹-A xilinx project, do it yourself, is mainly a dynamic display box on the VGA, freedom of movement on the screen, snags a rebound
piso1
- The following thesis describes the design, the synthesis, and the implementation of pulse width modulation (PWM) in Xilinx Field Programmable Gate Array (FPGA). The contribution of this thesis is the development of PWM in Xilinx
Real-time User Adjustable Video Filtering
- Real-time User Adjustable Video Filtering aim is to create an embedded system that demonstrates real-time video filtering using a Xilinx Virtex II multimedia board
sha1_v01
- sha1_testbench.v -- Testbench with vectors NIST FIPS 180-2 sha1_exec.v -- Top level sha1 module sha1_round.v -- primitive sha1 round dffhr.v -- generic parameterizable D-flip flop library Performance Analysis Performance equa
thesis
- thesis for simple virus detection processor which is developed in xilinx
library-IEEE
- pid controller design for implementation in xilinx for controlling dc motor speed using feedback which is obtained through optical sensor -pid controller design for implementation in xilinx for controlling dc motor speed using feedback which is obta
Tutorial_virtex7
- This a simple chip test program for Xilinx Virtex7. -This is a simple chip test program for Xilinx Virtex7.
ISE_TOOL_FLOW
- This Document Perhaps is the Xilinx Work flow under the Xilinx Environment FPGA Architecture
DSP-with-FPGAs
- Field-programmable gate arrays (FPGAs) are on the verge of revolutionizing digital signal processing in the manner that programmable digital signal processors (PDSPs) did nearly two decades ago. Many front-end digital signal processing (DSP) algo
axi-timer
- 这是Xilinx AXI定时器的说明手册，对于进行FPGA开发的工程师有参考价值 -The LogiCORE IP AXI Timer/Counter is a 32/ 64-bit timer module that interfaces to the AXI4-Lite interface.
coolrunner-ii_sch
- 基于CPLD的XILINX的系统设计，很适合初学者参考。-XILINX CPLD-based system design, it is suitable for beginners reference.