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devider_design
- Abstract循序电路第一个应用是拿来做计数器((笔记) 如何设计计数器? (SOC) (Verilog) (MegaCore))，有了计数器的基础后，就可以拿计数器来设计除频器，最后希望能做出能除N的万用除频器。-Abstract The first application of sequential circuits are used to make counter ((notes) How to design a counter? (SOC) (Verilog) (MegaCore)),
Verilog-HDL-standard
- VERILOG的编码设计规范，使你的程序容易被理解，阅读和维护-VERILOG coding design specifications, to make your program easier to understand, read and maintain
verilog-coding-rules
- Verilog HDL可综合RTL级代码设计规范及风格-Verilog HDL RTL level code design specifications and style
filter
- verilog—FIR滤波器程序，可移植性强，可以借助FDAtool设计滤波器系数，写到本程序里即可-verilog-FIR filter process, portability, and can make use of FDAtool design filter coefficients, the program can be written to
CPU
- 基于FPGA控制的ASIC CPU系统设计，全是用VERILOG代码编写，可以做加减乘除运算 -FPGA-based control ASIC CPU system design, all made with VERILOG code writing, arithmetic operations can be done
verilog
- 语言设计，虚拟器件，有限状态机，verilong语言教程等-Virtual Appliance
verilog_RS232
- 基于FPGA的Verilog硬件描述语言的串口通信设计，非常适合初学者和正在开发的人员使用，参考。-Descr iption Language Verilog FPGA-based hardware serial communication design, ideal for beginners and are being developed to use and reference.
dianzhen
- 如果需要用verilog设计一项比较简单的功能，那么这个浅显易懂的程序能让你很快明白点阵的设计方法，尤其是对那些初学者-If you need to use a relatively simple verilog design features, then this easy to understand design of the program allows you to quickly understand the lattice method, especially for those w
verilog2014
- verilog数字系统设计教程的教学ppt，包括基础知识，还有一些程序可供参考使用。-Verilog Teaching Digital System Design Tutorial ppt
hardwired
- 掌握硬连线控制器的设计方法。掌握硬连线控制器的Verilog HDL描述方法。了解QUARTUS II硬件描述语言和原理图混合输入设计的过程。 -Master the design method of hard wired controller. Grasp the hard wired controller Verilog HDL descr iption method. To understand the process of QUARTUS II hardware descr ipti
verilog
- verilog设计练习进阶，很不错的东西，有兴趣的可以下载-Advanced verilog design practice, very good things, are interested can download
FPGA-design-of-wavelet-filter
- 基于Verilog的小波滤波器程序设计的总结文档。-Verilog based wavelet filter program design summary document.
Verilog-DATAS-xiayuwen
- 3.1 引言 3.2 Verilog HDL基本结构 3.3 数据类型及常量、变量 3.4 运算符及表达式 3.5 语句 3.6 赋值语句和块语句 3.7 条件语句3.8 循环语句 3.9 结构说明语句 3.10 编译预处理语句 3.11 语句的顺序执行与并行执行 3.12 不同抽象级别的Verilog HDL模型 3.13 设计技巧-3.1 Introduction 3.2 Verilog HDL basic structure 3.3