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NRS4000_cpu
- 现代先进微处理器有非常高的集成度和复杂度,又有寄存器堆、Cache等嵌入式部件,而且芯片管脚数相对较少,必须要有一定的自测试设计和其它的可测试性设计来简化测试代码,提高故障覆盖率。本文简要讨论NRS4000微处理器芯片的以边界扫描测试为主体,以自测试为补充的可测试性设计框架。着重介绍芯片的边界扫描设计和芯片中译码控制器PLA和微程序ROM以及采用内嵌RAM结构的指令Cache和寄存器堆的内建自测试设计。仿真结果表明,这些可测试性设计大大缩短了测试代码的长度。-modern microproces
thesis04_dul98
- LDPC decoder thesis with development details
DEv_LDPC
- Development of LDPC Encoder/Decoder core
spra686
- Reed Solomon Decoder: TMS320C64x Implementation
LTU-EX-02289-SE
- Power consumption of Reed-Solomon decoder algorithms.
04375806
- DESIGN AND IMPLEMENTATION OF A MULTITHREADED HIGH RESOLUTION MPEG4 DECODER ON SANDBLASTER DSP
RF-TX-a-RX--ENCODER-DECODER
- Radio freuency transmitter and receiver
RS
- RS编码英文论文Reed-Solomon Decoder Hardware Implemented in FPGAs: A Prospectus -Reed-Solomon Decoder Hardware Implemented in FPGAs: A Prospectus
Interpolation-Technique-for-WZVC
- The manuscr ipt describes performance comparison of nearest-neighbor interpolation and bilinear to reduce the complexity of decoder WZVC.
HIGH-8B_10B-DECODE-ASIC
- 本文重点研究了高速8b/10b解码器的设计与实现,在详细介绍了解码原理及 多种传统解码方案的基础上,采用流水线结构设计了高速8b/10b解码器。通过 仔细分析传统解码器的不足,精心设计流水线结构及触发器在关键路径上的插入 点,使得所设计电路的速度比传统解码器有了较大的提升。-This paper focuses on the 8b/l 0b decoder,including the decoding principles and a variety of decoding sc