High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data (SIMD) computational architecture— two 32-bit IEEE floating-point

this document describe method of binary multiplication of signed and unsigned integer. it represent also the booth algorithm wich compounded with shift and adder blocks this optimise the comsumption of the alu

this is my code for ALU 8 bit